Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 83
![Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC32AG20SG
Manufacturer Part Number
Z16FMC32AG20SG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC32AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC32AG20SG
Manufacturer:
Zilog
Quantity:
160
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Table 39. IRQ1 Enable High Bit Register (IRQ1ENH)
Table 40. IRQ1 Enable Low Bit Register (IRQ1ENL)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Note: PADxENH = Port A/D Bit[x] Interrupt Request Enable High Bit
Bits
Field
RESET
R/W
ADDR
Note: PAxENL – Port A/D Bit[x] Interrupt Request Enable Low Bit.
IRQ2 Enable High and Low Bit Registers
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
R/W
R/W
7
0
7
0
The IRQ2 enable high and low bit registers (see Tables 42 and 43) form a priority-encoded
enabling for interrupts in the Interrupt Request 2 Register. Priority is generated by setting
bits in each register. Table 41 describes the priority control for IRQ2.
Table 41. IRQ2 Enable and Priority Encoding
Note: x indicates the register bits from 0 through 7.
IRQ2ENH[x]
0
0
1
1
R/W
R/W
6
0
6
0
IRQ2ENL[x] Priority
R/W
R/W
5
0
5
0
0
1
0
1
P R E L I M I N A R Y
Disabled
Level 1
Level 2
Level 3
R/W
R/W
4
0
4
0
FF_E036H
FF_E037H
R/W
R/W
Z16FMC Series Motor Control MCUs
3
0
3
0
Description
Disabled
Low
Nominal
High
R/W
R/W
2
0
2
0
Product Specification
R/W
R/W
Interrupt Controller
1
0
1
0
R/W
R/W
0
0
0
0
61
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