Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 79
![Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC32AG20SG
Manufacturer Part Number
Z16FMC32AG20SG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC32AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC32AG20SG
Manufacturer:
Zilog
Quantity:
160
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Table 33. Interrupt Request 1 Register (IRQ1) and Interrupt Request 1 Set Register (IRQ1SET)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Field
RESET
R/W
ADDR
Note: IRQ1SET at address FF_E035H is write only and used to set the interrupts identified.
Bits
7:0
Interrupt Request 2 Register
Note:
Description
PADxI – Port A/D Pin x Interrupt Request
0 = No interrupt request is pending for GPIO port A/D pin x.
1 = An interrupt request from GPIO port A/D pin x is awaiting service. Writing 1 to these bits
resets them to 0.
Here x indicates the specific GPIO port pin number (0 through 7). PAD7I and PAD0I have inter-
rupt sources other than Port A and Port D as selected by the Port A Irq Mux registers. PAD7I is
configured to provide the comparator interrupt. PAD0I is configured to provide the OCD inter-
rupt.
R/W1C
PAD7I
PAD7I
W
7
0
0
These bits are set any time the selected port is toggled. The setting of these bits are not
affected by the associated interrupt enable bits.
The interrupt request 2 (IRQ2) Register (see Table 34) stores interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the CPU. If inter-
rupts are globally disabled (polled interrupts), the CPU reads the Interrupt Request 1
Register to determine, if any interrupt requests are pending. Writing 1 to the bits in this
register clears the interrupt. The bits of this register are set by writing 1 to the interrupt
request 2 set regsiter (IRQ2SET) at address
R/W1C
PAD6I
PAD6I
W
6
0
0
R/W1C
PAD5I
PAD5I
W
5
0
0
P R E L I M I N A R Y
R/W1C
PAD4I
PAD4I
W
4
0
0
FF_E034H
FF_E035H
FF_E039H
R/W1C
PAD3I
PAD3I
Z16FMC Series Motor Control MCUs
W
3
0
0
.
R/W1C
PAD2I
PAD2I
W
2
0
0
Product Specification
R/W1C
PAD1I
PAD1I
W
Interrupt Controller
1
0
0
R/W1C
PAD0I
PAD0I
W
0
0
0
57
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