Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 82

Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D

Z16FMC32AG20SG

Manufacturer Part Number
Z16FMC32AG20SG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet

Specifications of Z16FMC32AG20SG

Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16FMC32AG20SG
Manufacturer:
Zilog
Quantity:
160
Part Number:
Z16FMC32AG20SG
Manufacturer:
Zilog
Quantity:
10 000
Table 37. IRQ0 Enable Low Bit Register (IRQ0ENL)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7
6
5
4
3
2
1
0
IRQ1 Enable High and Low Bit Registers
Description
T2ENL
Timer 2 Interrupt Request Enable Low Bit
T1ENL
Timer 1 Interrupt Request Enable Low Bit
T0ENL
Timer 0 Interrupt Request Enable Low Bit
U0RENL
UART 0 Receive Interrupt Request Enable Low Bit
U0TENL
UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL
SPIENL
ADCENL
ADC Interrupt Request Enable Low Bit
I
SPI Interrupt Request Enable Low Bit
2
T2ENL
C Interrupt Request Enable Low Bit
R/W
7
0
The IRQ1 enable high and low bit registers (see Tables 39 and 40) form a priority-encoded
enabling for interrupts in the Interrupt Request 1 Register. Priority is generated by setting
bits in each register. Table 38 describes the priority control for IRQ1.
Table 38. IRQ1 Enable and Priority Encoding
Note: x indicates the register bits from 0 through 7.
IRQ1ENH[x]
0
0
1
1
T1ENL
R/W
6
0
IRQ1ENL[x] Priority
T0ENL
R/W
5
0
0
1
0
1
P R E L I M I N A R Y
U0RENL
Disabled
Level 1
Level 2
Level 3
R/W
4
0
FF_E033H
U0TENL
R/W
Z16FMC Series Motor Control MCUs
3
0
Description
Disabled
Low
Nominal
High
I2CENL
R/W
2
0
Product Specification
SPIENL
R/W
Interrupt Controller
1
0
ADCENL
R/W
0
0
60

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