Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 286

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Reading Memory CRC
Breakpoints
been received during a write operation. A debug read cycle will occur when the transmit-
ter is empty during a read operation.
Data read from or written to the OCD occurs one byte at a time. Therefore, memory read
and write operations occur one byte at a time. Operations that occur on multi-byte words
does not occur concurrently.
Because the Z16FMC contains such a large memory space and the debug interface is
serial, reading massive amounts of data during debugging can be time-consuming. The
OCD hardware is capable of calculating a cyclic redundancy check (CRC) on memory to
allow memory-caching mechanisms to be used by the host debugging software. This CRC
verifies that the contents of a memory cache have not changed.
When the read CRC command is issued, the OCD hardware steals the CPU bus during the
entire Read operation. The length of time it takes to generate the CRC is equal to the
amount of time it takes to read the memory used in the CRC calculation.
The OCD hardware is also capable of returning separate CRCs for each 4K block of mem-
ory. These CRCs are used by software to determine the portions of memory which have
been modified when the cache for a large block of memory is invalidated.
Software Breakpoints
Breakpoints are generated when the CPU executes the
enabled. If breakpoints are not enabled, the
exception vector and set the illegal instruction status bit.
If a Breakpoint is generated, the OCD is configured to automatically enter Debug Halt
mode or to just loop on the instruction. If the OCD is configured to loop on the instruction,
the CPU is still able to service DMA and interrupt requests in the background. Software
polls the
Breakpoint.
Hardware Breakpoint
There are four hardware breakpoints on the Z16FMC device. When enabled, a breakpoint
is generated when the program counter matches the value in the breakpoint register, or
when a memory access occurs at the address in the breakpoint register. A data watchpoint
watches a range of addresses by selecting how many lower address bits are ignored.
DBGBRK
bit of the DBGCTL register to determine if the OCD has reached a
P R E L I M I N A R Y
BRK
Z16FMC Series Motor Control MCUs
instruction will vector to the system
BRK
instruction and breakpoints are
Product Specification
On-Chip Debugger
264