Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 181

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
ESPI Interrupts
DMA Interface
while SS is asserted and between the previous SCK edge and SS deassertion. A timeout
indicates the master is stalled or disabled. Writing 1 to ABT clears this error flag.
ESPI has a single interrupt output which is asserted when any of the
ABT
tion of one system clock) generated when any one of the source bits initially set. The
TDRE and RDRF interrupts are enabled/disabled through the Data Interrupt Request
Enable (
A transmit interrupt is asserted by the
the
transmit data register is written or the ESPI block is disabled. When the Transmit Data
Register value is loaded into the shift register to start a new transfer, the TDRE bit will be
set again causing a new transmit interrupt. If information is being received but not trans-
mitted the transmit interrupts are eliminated by selecting RECEIVE ONLY mode
(
(Transmit) data register is still required to initiate the transfer of a character.
A receive interrupt is generated by the RDRF status bit when the ESPI block is enabled;
the
the contents of the shift register is transferred into the Receive Data Register, causing the
RDRF
information is being transmitted but not received by the software application, the receive
interrupt is eliminated by selecting Transmit Only mode (
MASTER or SLAVE modes.
ESPI error interrupts occur if any of the
Register are set. These bits are cleared by writing a 1 to the corresponding bit.
If the ESPI is disabled (
out. This timer function must be enabled by setting the
ter. This timer interrupt does not set any of the bits of the ESPI Status Register.
The assertion of the TDRE and RDRF signals generate transmit and receive DMA
requests (SPITxReq, SPIRxReq), allowing data movement to be handled by a DMA con-
troller rather than directly by software. The DMA acknowledges these requests through
the SPITxAck and SPIRxAck signals). Inputs allow the
Data Command register to be controlled by the DMA. The SPITxReqEOF and
SPIRxReqEOF outputs to the DMA provides an indication that SS has deasserted (trans-
action complete).
If the software application is moving data in only one direction, the
set to 10 or 01, allowing a single DMA channel to control the ESPI data transfer. For a
ESPIEN1,0 = 01
DIRQE
DIRQE
,
ROVR
bit to assert. The
DIRQE
, or
bit is set and a character transfer completes. At the end of the character transfer,
bit is set. The
RDRF
) bit of the ESPI control register.
). A master operates in Receive Only mode however a write to the ESPI
bits are set in the ESPI status register. The interrupt is a pulse (dura-
RDRF
ESPIEN1,0 = 00
TDRE
P R E L I M I N A R Y
bit is cleared when the Receive Data Register is read. If
bit in the status register is cleared automatically when the
TDRE
TUND
), an ESPI interrupt is generated by a BRG time-
status bit when the ESPI block is enabled and
,
COL
Z16FMC Series Motor Control MCUs
,
ABT
Enhanced Serial Peripheral Interface
BRGCTL
SSV
and
ESPIEN1,0 = 10
and
ROVR
bit in the ESPICTL Regis-
TEOF
Product Specification
bits in the ESPI Status
ESPIEN1,0
TDRE
bits of the Transmit
,
) in either
TUND
,
bits are
COL
,
159