HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 41

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 19.
Default settings are shown highlighted.
Table 20.
Default settings are shown highlighted.
Table 21.
Table 22.
Table 23.
DAC1408D650
Product data sheet
Bit
1 to 0
Bit
7
6
5
4 to 3
2 to 1
0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Symbol
INT_FIR[1:0]
Symbol
PLL_PD
-
-
PLL_DIV[1:0]
PLL_PHASE[1:0]
PLL_POL
Symbol
FREQ_NCO[7:0]
Symbol
FREQ_NCO[15:8]
Symbol
FREQ_NCO[23:16]
TXCFG register (address 01h) bit description
PLLCFG register (address 02h) bit description
FREQNCO_LSB register (address 03h) bit description
FREQNCO_LISB register (address 04h) bit description
FREQNCO_UISB register (address 05h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
Access
R/W
Access
R/W
…continued
Value
00
01
10
11
Value
0
1
0
0
00
01
10
00
01
10
11
0
1
Value
66h
Value
66h
Value
66h
2, 4 or 8 interpolating DAC with JESD204A
Description
interpolation
Description
PLL
undefined
must be written with ’0’
PLL divider factor
PLL phase shift of f
clock edge of DAC (f
Description
lower 8 bits for the NCO frequency setting
Description
lower intermediate 8 bits for the NCO frequency
setting
Description
upper intermediate 8 bits for the NCO frequency
setting
no interpolation
2
4
8
switched on
switched off
2
4
8
0
120
240
undefined
normal
inverted
DAC1408D650
s
s
)
© NXP B.V. 2010. All rights reserved.
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