HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 77

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

Table 143. Page 6 register allocation map
Address
0
1
2
3
4
5
6
7
8
9
10 0Ah
11 0Bh
12 0Ch
13 0Dh
16 10h
17 11h
18 12h
19 13h
20 14h
21 15h
22 16h
23 17h
24 18h
25 19h
26 1Ah
27 1Bh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
10.15.2.11 Page 6 allocation map description
Register name
LN0_CFG_0
LN0_CFG_1
LN0_CFG_2
LN0_CFG_3
LN0_CFG_4
LN0_CFG_5
LN0_CFG_6
LN0_CFG_7
LN0_CFG_8
LN0_CFG_9
LN0_CFG_10
LN0_CFG_11
LN0_CFG_12
LN0_CFG_13
LN1_CFG_0
LN1_CFG_1
LN1_CFG_2
LN1_CFG_3
LN1_CFG_4
LN1_CFG_5
LN1_CFG_6
LN1_CFG_7
LN1_CFG_8
LN1_CFG_9
LN1_CFG_10
LN1_CFG_11
R/W Bit definition
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
b7
LN0_SCR
LN1_SCR
LN0_HD
LN1_HD
-
-
-
-
-
-
-
-
-
-
LN0_CS[1:0]
LN1_CS[1:0]
b6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
b5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
b4
LN0_RES1[7:0]
LN0_RES2[7:0]
LN0_FCHK[7:0]
LN1_RES1[7:0]
-
-
LN0_DID[7:0]
LN1_DID[7:0]
LN0_M[7:0]
LN1_M[7:0]
LN0_F[7:0]
LN1_F[7:0]
b3
LN0_LID[4:0]
LN1_LID[4:0]
b2
LN0_CF[4:0]
LN1_CF[4:0]
LN0_N’[4:0]
LN1_N’[4:0]
LN0_K[4:0]
LN0_N[4:0]
LN0_S[4:0]
LN1_K[4:0]
LN1_N[4:0]
LN1_S[4:0]
LN0_L[4:0]
LN1_L[4:0]
LN0_BID[3:0]
LN1_BID[3:0]
b1
b0
Default
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