HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 62

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 89.
Table 90.
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
7 to 4
3 to 0
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Symbol
MAN_ALIGN_LN3[3:0]
MAN_ALIGN_LN2[3:0]
Symbol
SEL_KOUT_ UNEXP_LN23[1:0]
SEL_KOUT_ UNEXP_LN10[1:0]
SEL_NIT_ERR_ LN23[1:0]
SEL_NIT_ERR_ LN10[1:0]
MAN_ALIGN_LN_2_3 register (address 0Ah) bit description
FA_ERR_HANDLING register (address 0Bh) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
Access
R/W
R/W
R/W
R/W
Value
0h
0h
Value
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
2, 4 or 8 interpolating DAC with JESD204A
Description
indicates alignment data-delay for lane 3 [1..15]
indicates alignment data-delay for lane 2 [1..15]
Description
lane 2/lane 3 unexpected /K/ error handling
lane 0/lane 1 unexpected /K/ error handling
lane 2/lane 3 nit-error handling
lane 0/lane 1 nit-error handling
unexpected /K/ in lane 2 or lane 3
error_handling
unexpected /K/ in lane 2 and lane 3 error_handling
unexpected /K/ in lane 2 error_handling
unexpected /K/ in lane 3 error_handling
unexpected /K/ in lane 0 or lane 1
error_handling
unexpected /K/ in lane 0 and lane 1 error_handling
unexpected /K/ in lane 0 error_handling
unexpected /K/ in lane 1 error_handling
nit-errors in lane 2 or lane 3 error_handling
not-in-table errors lane 2 and lane 3
error_handling
not-in-table errors in lane 2 error_handling
not-in-table errors in lane 3 error_handling
nit-errors in lane 0 or lane 1 error_handling
not-in-table errors lane 0 and lane 1
error_handling
not-in-table errors in lane 0 error_handling
not-in-table errors in lane 1 error_handling
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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