HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 49

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 54.
Default settings are shown highlighted.
Table 55.
Default settings are shown highlighted.
Table 56.
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
4
3 to 0
Bit
6 to 0
Bit
7
6
5
4
3
2
1
0
Symbol
MDS_RELOCK
MDS_LOCK_DELAY[3:0]
Symbol
MDS_ADJDELAY[6:0]
Symbol
EARLY
LATE
EQUAL
MDS_LOCK
EARLY_ERROR
LATE_ERROR
EQUAL_FOUND
MDS_ACTIVE
MDS_MISCCNTRL1 register (address 06h) bit description
MDS_ADJDELAY register (address 08h) bit description
MDS_STATUS0 register (address 09h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
Access
R
Access
R
R
R
R
R
R
R
R
Value
0
1
Fh
Value
-
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2, 4 or 8 interpolating DAC with JESD204A
Description
number of succeeding 'equal'-detections until lock
Description
actual value adjustment delay
Description
early signal (sampled) from early-late detector
late signal (sampled) from early-late detector
equal signal (sampled) from early-late detector
result equal check
adjustment delay maximum value stops the search
adjustment delay minimum value stops the search
evaluation logic has detected equal condition
evaluation logic active
relock mode
…continued
no action
relock when lockout occurs
false
true
false
true
false
true
false
true
false
true
false
true
false
true
false
true
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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