HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 79

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 144. LN0_CFG_0 register (address 00h) bit description
Default settings are shown highlighted.
Table 145. LN0_CFG_1 register (address 01h) bit description
Default settings are shown highlighted.
Table 146. LN0_CFG_2 register (address 02h) bit description
Default settings are shown highlighted.
Table 147. LN0_CFG_3 register (address 03h) bit description
Default settings are shown highlighted.
Table 148. LN0_CFG_4 register (address 04h) bit description
Default settings are shown highlighted.
Table 149. LN0_CFG_5 register (address 05h) bit description
Default settings are shown highlighted.
Table 150. LN0_CFG_6 register (address 06h) bit description
Default settings are shown highlighted.
Table 151. LN0_CFG_7 register (address 07h) bit description
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
7 to 0
Bit
3 to 0
Bit
4 to 0
Bit
7
4 to 0
Bit
7 to 0
Bit
4 to 0
Bit
7 to 0
Bit
7 to 6
4 to 0
Symbol
LN0_DID[7:0]
Symbol
LN0_BID[3:0]
Symbol
LN0_LID[4:0]
Symbol
LN0_SCR
LN0_L[4:0]
Symbol
LN0_F[7:0]
Symbol
LN0_K[4:0]
Symbol
LN0_M[7:0]
Symbol
LN0_CS[1:0]
LN0_N[4:0]
10.15.2.12 Page 6 bit definition detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 143
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R
Access
R
Access
R
Access
R
R
Access
R
Access
R
Access
R
Access
R
R
for a register overview and their default values. In the following
Value
-
Value
-
Value
-
Value
-
-
Value
Value
-
Value
-
Value
-
-
-
2, 4 or 8 interpolating DAC with JESD204A
Description
lane 0 device ID
Description
lane 0 bank ID
Description
lane 0 lane ID
Description
scrambling on
number of lanes minus 1
Description
Description
number of frames per multi-frame minus 1
Description
number of converters per device minus 1
Description
number of control bits
converter resolution minus 1
number of octets per frame minus 1
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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