KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 135

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

4) See additional document “TC1767 Pin Reliability in Overload“ for definition of overload current on digital pins.
5) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to
6) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
7) Applicable for digital outputs.
Table 9
Group
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Data Sheet
the resulting leakage current (IleakTOT) into an adjacent pin: IleakTOT = ±kA × |IOV| + IOZ1.
Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent
analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN ×
|IleakTOT|.
The definition of adjacent pins is related to their order on the silicon.
The Injected leakage current always flows in the opposite direction from the causing overload current.
Therefore, the total leakage current must be calculated as an algebraic sum of the both component leakage
currents (the own leakage current IOZ1 and the optional injected leakage current).
parameters.
Pins
P4.[7:0]
P4.[15:8]
P10.[5:0]
P15.[0, 1, 7:4, 11, 12]
P15.[3:0, 8, 13], P16.3
P15.9, P16.2, P15.10, P15.[15:14]
P14.[15:10]
P14.[9:8]
P14.[7:2]
P14.[1:0], P13.[15:14]
P13.[13:12]
P13.[11:6]
P13.[5:2]
P13.[1:0], P12[5:4]
P12.[3:0]
P11.[15:12]
P11.[11:8]
P11.[7:4]
P11.[3:0]
P12.[7:6]
Pin Groups for Overload / Short-Circuit Current Sum Parameter
131
Electrical Parameters
V1.1, 2009-04
TC1797