KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 182

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

5.3.11.3 SSC Master/Slave Mode Timing
Table 31
Parameter
Master Mode Timing
SCLK clock period
MTSR/SLSOx delay from
SCLK rising edge
MRST setup to SCLK
falling edge
MRST hold from SCLK
falling edge
Slave Mode Timing
SCLK clock period
SCLK duty cycle
MTSR setup to SCLK
latching edge
MTSR hold from SCLK
latching edge
SLSI setup to first SCLK
shift edge
SLSI hold from last SCLK
latching edge
MRST delay from SCLK
shift edge
SLSI to valid data on MRST
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 ×
3)
4) Fractional divider switched off, SSC internal baud rate generation used.
Data Sheet
T
SSCmin
=
T
SYS
SSC Master/Slave Mode Timing
(Operating Conditions apply), C
= 1/
f
SYS
. When
f
SYS
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
= 90 MHz,
50
51
52
53
54
55
56
57
58
59
60
61
/
t
54
CC
CC 2 ×
SR 13
SR 0
SR 4 ×
SR
SR
SR
SR 7
CC 0
CC –
SR 45
t
50
= 22.2 ns.
Min.
0
T
T
T
178
SSC
SSC
SSC
T
T
T
SSC
SSC
SSC
+ 5
+ 5
+ 5
L
= 50 pF
.
Values
Typ. Max.
–
–
–
–
–
–
–
–
–
–
–
–
–
8
–
–
–
55
–
–
–
–
15
12
Electrical Parameters
Unit Note /
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
V1.1, 2009-04
Test Con
dition
1)2)3)
–
3)
3)
1)3)
–
3)4)
3)4)
3)
–
–
–
TC1797