KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 160
KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 160 of 190
- Download datasheet (6Mb)
With rising number
of
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency
Figure 27
Figure 27
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
Data Sheet
m
D
m
±10.0
that is defined by the K2-factor of the PLL. Beyond this value of
±4.0
±2.0
±0.0
±8.0
±7.0
±6.0
±1.0
not exceed
output pins, which can be loaded with
many pins with high loads, driver strengths and toggle rates the specified jitter
values could be exceeded.
V
V
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V
V
ns
DDOSC3
PP
DDOSC
PP
0
= 100 mV for noise frequencies below 300 KHz and
= 100 mV for noise frequencies below 300 KHz and
f
gives the jitter curves for several K2 /
D
m
K2
LMB
m
= Max. jitter
= Number of consecutive f
= K2-divider of PLL
at pin F26 and
Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies
at pin E26 and
results in a higher absolute maximum jitter value.
C
L
m
20
= 20 pF with the maximum driver and sharp edge, except the E-Ray
of clock cycles the maximum jitter increases linearly up to a value
f
LMB
= 50 MHz (K2 = 8)
V
V
f
40
LMB
SSOSC
SSOSC
= 50 MHz (K2 = 16)
f
LMB
f
LMB
LMB
at pin F25, is limited to a peak-to-peak voltage of
at pin F25, is limited to a peak-to-peak voltage of
= 100 MHz (K2 = 4)
= 100 MHz (K2 = 8)
periods
f
LMB
60
156
C
L
f
f
LMB
LMB
= 25 pF. In case of applications with
80
= 150 MHz (K2 = 4)
combinations.
f
LMB
= 180 MHz (K2 = 4)
100
Electrical Parameters
V
V
PP
PP
TC1797_PLL_JITT_M
= 40 mV for noise
= 40 mV for noise
m
120
the maximum
V1.1, 2009-04
TC1797
o
m
o
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