KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 164
KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 164 of 190
- Download datasheet (6Mb)
5.3.8
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
Table 22
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
TDO valid after TCK falling
edge
TDO hold after TCK falling
edge
TDO high imped. to valid
from TCK falling edge
TDO valid to high imped.
from TCK falling edge
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
1)
1)
characterization.
(propagation delay)
JTAG Interface Timing
JTAG Interface Timing Parameters
(Operating Conditions apply)
1)2)
1)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
8
18
9
10
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
Min.
25
12
10
–
–
6
6
–
–
2
–
–
160
Values
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
–
4
4
–
–
13
3
–
14
13.5
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Electrical Parameters
Test Condition
–
–
–
–
–
–
–
C
C
C
C
L
L
L
L
= 50 pF
= 20 pF
= 50 pF
= 50 pF
V1.1, 2009-04
TC1797
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