KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 162
KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 162 of 190
- Download datasheet (6Mb)
5.3.6
Note: All PLL characteristics defined on this and the next page are not subject to
Table 20
Parameter
Accumulated jitter at
E_Ray module clock input
Accumulated jitter at
SYSCLK pin
VCO frequency range
VCO input frequency range
PLL base frequency
PLL lock-in time
1) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with
2) Short term jitter and long term jitter for all numbers P of sample clocks (P ≥ 1), with
3) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
Data Sheet
f
f
the K factor after reset).
SAMPLE
SAMPLE
production test, but verified by design characterization.
not exceed
output pins, which can be loaded with
many pins with high loads, driver strengths and toggle rates the specified jitter
values could be exceeded.
V
V
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
V
V
frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
DDPF3
PP
DDPF
PP
= 80 MHz.
= 80 MHz.
= 100 mV for noise frequencies below 300 KHz and
= 100 mV for noise frequencies below 300 KHz and
E-Ray Phase Locked Loop (E-Ray PLL)
2)
at pin G23 and
at pin G24 and
PLL Parameters of the System PLL(Operating Conditions apply)
C
L
3)
= 20 pF with the maximum driver and sharp edge, except the E-Ray
1)
Symbol
D
D
f
f
f
t
V
VCO_ERAY
REF_ERAY
PLLBASE_ERAY
L_ERAY
V
P_ERAY_I
P_ERAY_E
SSOSC
SSOSC
at pin F25, is limited to a peak-to-peak voltage of
at pin F25, is limited to a peak-to-peak voltage of
158
Min.
–
–
400
20
140
–
C
L
= 25 pF. In case of applications with
Values
Typ. Max.
–
–
–
–
–
–
0.5
0.8
500
40
320
200
Electrical Parameters
V
V
PP
PP
f
f
OSC
OSC
= 40 mV for noise
= 40 mV for noise
Unit Note /
ns
ns
MHz –
MHz –
MHz –
µs
= 20MHz, K = 6, and
= 20MHz, K = 6, and
V1.1, 2009-04
Test Con
dition
–
–
–
TC1797
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