LH28F160BVE-BTL90 Sharp Electronics, LH28F160BVE-BTL90 Datasheet

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LH28F160BVE-BTL90

Manufacturer Part Number
LH28F160BVE-BTL90
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F160BVE-BTL90

Cell Type
NOR
Density
16Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
21/20Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
2M/1M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant

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LH28F160BVE-BTL90
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SHARP
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LH28F160BVE-BTL90
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SHARP
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LH28F160BVE-BTL90
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SHARP
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P
S
RODUCT
PECIFICATIONS
Integrated Circuits Group
®
LH28F160BVE-BTL90
Flash Memory
16M (2M × 8/1M × 16)
(Model No.: LHF16V09)
Spec No.: EL10Y075A
Issue Date: September 7, 1999

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LH28F160BVE-BTL90 Summary of contents

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... P S RODUCT PECIFICATIONS LH28F160BVE-BTL90 16M (2M × 8/1M × 16) ® Flash Memory (Model No.: LHF16V09) Spec No.: EL10Y075A Issue Date: September 7, 1999 Integrated Circuits Group ...

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SHARB= l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered ...

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SHARP 1 INTRODUCTION.. ........................................................... . Features ....................................................................... 1.2 Product Overview.. ....................................................... 3 2 PRINCIPLES OF OPERATION ....................................... .7 2.1 Data Protection. ............................................................ 3 BUS OPERATION ........................................................... .8 3.1 Read.. ........................................................................... 3.2 Output Disable.. ........................................................... 3.3 Standby.. ....................................................................... 3.4 ...

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... Not designed or rated as radiation hardened low-cost, can operate at V,,- -2.7V-3.6V architecture, flexible voltage and extended and personal computers. Its enhanced suspend capabilities For secure code storage applications, to DRAM, the LH28F160BVE-BTL90 on SHARP’s 0.35pm ETOXTM* 16) x Features with Vpp=GND Write Lockout with WP#=VlL ...

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... This datasheet contains LH28F160BVE-BTL90 specifications. Section 1 provides a flash memory overview. Sections 2,3,4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of LH28F160BVE-BTL90 memory are: l 2.lV-3.6V V,, and V,, Read/Write/Erase *Enhanced Suspend Capabilities *Boot Block Architecture Please note following ...

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SHARP The boot blocks can be locked for the WP# pin. Block erase or word/byte write for boot block must not be carried out by WP# to Low and RP# to VI,. The status register indicates when the WSM’s or ...

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SHARP - ho AIS = 1 A14 / A13 = 4 A12 & ‘ A19 NC 10 WE# 11 RP# 12 VPP WP# RYfBY AIS ...

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... SUPPLY VW word/byte write with an invalid V,, (see DC Characteristics) not be attempted. DEVICE POWER SUPPLY: Do not float any power pins. With V,,IV,K,, SUPPLY the flash memory are inhibited. Device operations at invalid V,, vcc produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. ...

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... SHARP 2 PRINCIPLES OF OPERATION The LH28F160BVE-BTL90 Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for: 100% ITL-level fixed power supplies during block erasure and word/byte write, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power- down mode (see Bus Operations), the device defaults to read array mode ...

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... Refer to Table 6 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read lnformation can be read from any block, identifier codes or status register independent of the V, at either V,, or V,, ...

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SHARP 3.5 Read Identifier Codes Operation The read identifier codes operation manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. L%P-Aol FFFFF Reserved ...

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SHARP Notes Mode Read 8 Output Disable Standby 10 Deep Power-Down 4,lO Read Identifier Codes 8 Write 6,728 Deep Power-Down 4,lO Read Identifier Codes 899 67 8 Write 1 1 rlOTES: . Refer to DC Characteristics. When V,,IV,,,,, !. X ...

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SHARP Bus Cycles Rea’d. Write Resume VOTES: 1. BUS operations are defined in Table 3.1 and Table 3.2. 2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. A-, set to V,, or V,, in Byte Mode ...

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Read Array Command 1 Jpon initial device power-up and after exit from deep Jower-down mode, the device defaults to read array mode. I’his operation is also initiated by writing the Read Array :ommand. The device remains enabled for reads ...

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... Rp#=V,,. suspended are Read Status Register and Block Resume. After a Block Erase Resume command is written SR. 1 and SR.4 will to the flash memory, the WSM will continue the block operations with erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After ...

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... Vpp=V1~ for Complete Protection The V,, complete write protection of all blocks in the flash device. 4.10.2 WP#=VIL for Block Locking The lockable blocks are locked when WP#=V,,; program or erase operation to a locked block will result in an error, which will be reflected in the status register. For is top configuration, the top two boot blocks are lockable ...

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SHARP ESS WSMS / 6 7 SR.7 = WRITE STATE MACHINE 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 ...

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SHARP r Check if Desired FULL STATUS CHECK PROCEDURE Read Status Register DataWee Above) Device Protect Block Erase Error Block Erase Successful LHF16V09 Suspend Block Standby Erase Loop Full s,a,us cheek CM be done block erasores. Write FFH after the ...

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SHARP Write 40H or lOH, Address write word/Byte Data and Address I Check if Desired FULL STATUS CHECK PROCEDURE Read Status Register Dal&See Above) Vpp Range Error LHF16V09 Write setup wordiByle Write word/Byte Standby Rcpca, for subsequent byte writes. SR ...

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SHARP * Block Erase Completed Read Array Data word/Byte write Loop Figure 7. Block Erase Suspend/Resume Flowchart LHFl6VO9 BUS Command Opzration Dala=BOH Addr=X Stmtus Register Data Addr=X Check SR.7 l=WSM Ready &WSM Check SR.6 I=Blwk O=Block Erase ...

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SHARP word/Byte write Completed Figure 8. Word/Byte Write Suspend/Resume Flowchart LHF16V09 Bus Command Operaion Data=BOH Ad&= Status Register Data Read Addr=X Rev. 1.1 ...

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... Vpp Trace on Printed Circuit Boards should also Updating flash memories that reside in the target systerr requires that the printed attention to the V,, supplies the memory cell current for word/byte and block erasing. Use similar considerations supply traces and decoupling write completion ...

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... When designing portable systems, designers must consider battery power operation, but also for data retention during system idle time. Flash battery life because data is retained when system power is removed. In addition, deep power-down low power consumption applied. For example, portable computing products and ...

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SHARP 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, BIock Erase and Word/Byte Write . . . . . . . . . . . . . . . . . . . . . . . ...

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SHARP 6. 2.2 AC INPUT/OUTPUT TEST CONDITIONS AC test inputs are driven at 2.7V for a Logic “1” and O.OV for a Logic “0.” Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to ...

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SHARP 5.2.3 DC CHARACTERISTICS Sym. Parameter Input Load Current IL1 Output Leakage Current IL0 Vcc Standby Current kcs Vcc Deep Power-Down Current ‘CCD Vcc Read Current ‘CC, V,, Word/Byte Write Current kcw V,, Block Erase Current ‘CCE kcws Vcc Word/Byte ...

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SHARI= F Sym. VlL VIH VOL Output High Voltage VP, Lockout Voltage during Normal Operations VP, Voltage during Word/Byte Write or Block Erase Operations VP, Voltage during Word/Byte Write or Block Erase Operations V,, Lockout Voltage RP# Unlock Voltage NOTES: ...

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SHARP 6.2.4 AC CHARACTERISTICS Svm. I OE# to Output Delay c3LOV CE# to Output in Low Z tELOX t,,.,, to Outnut High Z - -..= -.. -.. -~~_~~ - CE# Hiph in -ctlv15 I --.. ---a OE# tn ...

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Standby Address Selection VIH \DDRESSES(A) VIL VIH CEW) VIL VIH OE#(G) VIL VIH WE#(W) VIL VOH DATA(DIQ) PQo-WIS) VOL vcc VIH RP#(P) VI, Figure 11. AC Waveform for Read Operations LHF16V09 Device Data Valid 27 Rev. 1.1 ...

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SHARP Standby Address / VIH IDDRESSES \ VIL VIH CEW) VIL VIH OE#(G) VIL VIH BYTE#(F) VIL VOH HIGH Z DATA(DIQ) (DQo-DQ7) VOL . VOH HIGH Z DATA(D/Q) (DQs-DQIs) VOL LHFl6VO9 Devi c e Data Val i d Selection Address ...

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SHARP 6.2.5 AC CHARACTERISTICS NOTES: 1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 4 ...

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SHARP VIH ADDRESSES(A) VIL CE#(E) VIH VIH DATA(D/Q) VIH RY/BY#(R) VHH RWP) NOTES: 1. Vcc power-up and standby. 2. Write block erase or word/byte write setup. 3. Write block erase confirm or valid address 4. Automated erase or program delay. ...

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SHARP 6.2.6 ALTERNATIVE CE#-CONTROLLED NOTES systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% ...

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SHARP vIH ADDRESSES(A) "IL vIH CEW) VI, OE#(G) vIH WE#(W) “IL DATA(D/Q) BY?E#(F) RY/BY#(R) RWP) VPPW) NOTES: 1. VCC power-up and standby. 2. Write block erase or word/byte write setup. 3. Write block erase confirm or valid address 4. Automated ...

Page 35

SHARP 2.7 RESET OPERATIONS High Z RY/BY#(R) VOL VIH Rf’W’) VIL High 2 RY/BY#(R) VOL VIH RW’) VIL 2.w vcc VIL VIH RF’W’) VIL Sym. RP# Pulse Low Time ‘LPH this specification is not applicable) (If RP# is tied to ...

Page 36

SHARP 6.2.8 BLOCK ERASE AND WORD/BYTE Erase Suspend Latency Time to Read NOTES: 1. Typical values measured at TA=+25”C and V,,=3.W, device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. 4. All values are in word mode ...

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... Label Paper i ________________________________________----~---~--~~----------~~~---~~--~~-~~~-~~~~~-~~~~~~~~~--~~-~.~~-~-----------------~~~-------~~-------------- Outer case Card board :Devices shall be placed into a tray LHFl6VO9 14 2 LH28F160BVE-BTL90 SHARP w w xxx Indicates the product in the WWth week of 19YY. Denotes the product ion ref.code Denotes the production (01,02.03 ’ * 52,53) Denotes the production ...

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SHARP 3- 2. Outline dimension of tray Refer to attached drawing Storage and Opening of Dry Packing 4. 4-l. Store under conditions ( 1) Temperature range (2) Humidity 4-2. Notes on opening the dry packing (1) Before opening the dry ...

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... SHARP I 0 LH28F160BVE- SBTLSO SHARP JAPAN YYWW 2*L /SEE DETAIL A ia APANJ ~~ti~~~~o>~-3~%& NOTES : Marking specification when “JAPAN-is marked. m& KtiJz NAME f TSOP48-P-1220 LEAD FINISH ! PLATING NOTE Plastic body dimensions do not include burr w-ii DRAWING NO. i AA1142 UNIT 1 mm LHF16V09 ...

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SHARP LH28FMlBVE-B TL9 ZYYWW 24- 19.OfO. UJ APANJ ~~~ti~t~cl\~~~-~~r-ka Em? : NOTES : Marking specification when ‘JAPAN” is not marked Kf&Jz s%q NAME 1 TSOP48-P-1220 LEAD FINISH j PLATING NOTE Plastic body dimensions do not include burr em ...

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SHARP - - $i%! iAMEiTSOP48-1220TCM-RH w2 DRAWING NO. j CV756 UNIT LHF16V09 Me NOTE ...

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... Reflow soldering conditions Measurement point Storage conditions Note Recommnded Reflow SoIdering(Air) I LHF16V09 LHF16V09 for two time reflow soldering LH28F160BVE-BTL90 (TSOP48-P-1220) Tray (Dry packing) Reflow soldering (Air) Peak temperature of 230°C or less. of less 200°C or over, duration than 40 seconds. Preheat temperature of 12%150”C,duration than 180 seconds ...

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... Noises having a level exceeding generated under specific operating Such noises, when induced onto WE# signal or power supply, commands, causing undesired To protect the data stored in the flash memory against operating with the flash memory should have the following appropriate: 1) Protecting data in specific By setting ...

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... I RELATED DOCUMENT INFORMATION(*) No. Document AP-00 l-SD-E Flash Memory Family Software Drivers AP-006~FT-E Data Protection Method of SHARP Flash Memory RP#, VP,, Electric Potential Switching AP-007~SW-E NOTE : 1. International customers should contact their local SHARP or distribution Document Name Circuit sales office. ...

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SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all ...

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