LH28F160BVE-BTL90 Sharp Electronics, LH28F160BVE-BTL90 Datasheet - Page 22

• Manufacturer Part Number: LH28F160BVE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BVE-BTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

SHARP
The device will
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ#
This assures that only selected memory
active outputs while
standby mode. RP# should be connected
POWERGOOD
system power
toggle during system reset.
5.2 RY/BY#,
RY/BY# is an open drain output that should be connected
to V,,
of detecting block erase and word/byte
It transitions
commands and returns to High Z when the WSM
finished executing the internal algorithm.
RY/BY#
system CPU or controller.
is also High Z when the device is in block erase suspend
[with word/byte
ar deep power-down
5 DESIGN
5.1 Three-Line
SHARP
multiple memory connections. Three-line
for:
b. Complete assurance that data bus contention
a. Lowest possible memory power dissipation.
occur.
Write Polling
by a pulllup resistor to provide a hardware method
provides
can be connected to an interrupt
low after block erase or word/byte
CONSIDERATIONS
signal to prevent unintended writes during
transitions.
write inactive), word/byte
often be used in large memory arrays.
Block Erase and Word/Byte
three control
Output Control
modes.
deselected memory devices are in
It is active at all times. RY/BY#
POWERGOOD
inputs to accommodate
write completion.
control provides
to the system
write suspend
devices have
input of the
control
should
will not
write
line.
also
has
LHFl6VO9
capacitor
board trace inductance.
Updating
requires
attention
supplies the memory cell current for word/byte
and block erasing. Use similar
considerations
supply traces and decoupling
spikes and overshoots.
Flash memory
careful device decoupling.
in three supply current issues; standby current levels
active current levels and transient
falling and rising edges of CE# and OE#. Transient curren
magnitudes
inductive loading. Two-line
capacitor selection will
Each device should
connected between its V,,
and
capacitors should be placed as close as possible to package
leads. Additionally,
electrolytic capacitor should be placed at the array’s power
supply connection
5.4 Vpp Trace on Printed Circuit Boards
5.3 Power Supply Decoupling
GND.
that the printed
to the V,,
flash memories that reside in the target systerr
will
depend on the device outputs’ capacitive am
These
given to the V,,
overcome
power
between
for every eight
Power supply trace. The V,,
have a O.luF
high-frequency,
switching
suppress transient voltage peaks
voltage slumps caused by PC
System designers are interestec
and GND and between its V,,
control and proper decoupling
circuit
Vcc
will decrease V,,
power bus. Adequate V,,
trace widths and layoul
characteristics
and GND. The bulk
board
peaks produced
ceramic
devices, a 4.7pF
low
designer
inductance
capacitor
Rev. 1.1
voltage
writing
requin
pay
pir
20
bl