LH28F160BVE-BTL90 Sharp Electronics, LH28F160BVE-BTL90 Datasheet - Page 23

• Manufacturer Part Number: LH28F160BVE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BVE-BTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

SHARP
Block erase and word/byte write are not guaranteed if VP,
falls outside of a valid VPPH,,z range, V,,
a valid 2.lV-3.6V range, or RP##V,, or V,,.
is detected, status register bit SR.3 is set to “1” along with
SR.4 or SR.5, depending on the attempted operation. If
RP# transitions to V,, during block erase or word/byte
write, RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the device
will enter deep power-down.
leave data partially
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V,, clear
the status register.
The CUI latches commands issued by system software and
is not altered by VP, or CE# transitions or WSM actions.
Its state is read array mode upon power-up, after exit from
deep power-down
After block erase or word/byte
transitions down to VP,,,,
array mode via the Read Array command if subsequent
access to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed
accidental block erasure or word/byte
power
indifferent as to which power
powers-up first. Internal circuitry resets the CUI to read
array mode at power-up.
5.5 V,,, V,, RP# Transitions
transitions.
or after V,, transitions below V,,,.
Upon
altered. Therefore,
the CUI must be placed in read
to offer
power-up,
The aborted operation may
supply (V,
write, even after VP,
protection
the device
writing
falls outside of
the command
If VP, error
or V,,)
against
during
LHF16V09
is
In addition, deep power-down
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering Rp# to V,, standby or sleep modes. If
access is again needed, the devices can be read following
the
first raised to V,,. See AC Characteristics-
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
command sequence architecture provides added level 01
WP# provide additional protection from inadvertent code
regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must consider
battery
operation, but also for data retention during system idle
time. Flash
battery life because data is retained when system power is
removed.
low power consumption
A system designer must guard against spurious writes fol
V,,
WE# and CE# must be low for a command write, driving
either to V,,
protection against data alteration.
or data alteration. The device is disabled while RF%=V,,
tPHQV
voltages above V,,,
power
md
memory’s
tPHWL
will inhibit writes.
consumption
wake-up cycles required after RP# is
nonvolatility
even when system power is
when V,
not only during
mode ensures extremely
The GUI’s two-stel:
is active. Since bott
increases usable
Read Only
Rev. 1.1
device
21