LH28F160BVE-BTL90 Sharp Electronics, LH28F160BVE-BTL90 Datasheet - Page 10

• Manufacturer Part Number: LH28F160BVE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BVE-BTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

SHARP
choose
optimization of the processor-memory
When VppIVppLK,
The CUI, with two-step block erase or word/byte write
command sequences, provides protection from unwanted
operations even when high voltage is applied to V,,. All
write functions are disabled when V,,
lockout voltage VLKO or when RP# is at V,,. The device’s
boot
additional protection
alteration by block erase and word/byte write operations.
Refer to Table 6 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
lnformation can be read from any block, identifier codes
or status register independent of the V,
be
The first task is to write
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
ar after exit from deep power-down
automatically resets to read array mode. Six control pins
dictate the data flow in and out of the component: CE#,
3E#, WE#, RP#, WP# and BYTE#. CE# and OE# must be
lriven active to obtain data at the outputs. CE# is the
levice selection control, and when active enables the
selected memory
:DQ,-DQt5)
nemory data onto the I/O bus. WE# must be at V,, and
XP#/ must be at V,, or V,,.
:ycle.
2.1 Data Protection
Depending on the application, the system designer may
(available only when memory block erases or word/byte
writes are required) or hardwired to V,,,,,,.
accommodates
at either V,, or V,,.
blocks
to make the V,,
control and when active drives the selected
locking
either design practice
device.
memory contents cannot be altered.
from
capability
Figure 11, 12 illustrates read
the appropriate read mode
OE#
inadvertent
power
is the data output
for
interface.
supply
mode, the device
is below the write
voltage. RP# can
and encourages
WP#
code or data
The device
switchable
provides
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
during block erase or word/byte write modes. If a CPU
reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array data.
SHARP’s flash memories allow proper CPU initialization
following a system reset through the use of the RP# input.
In this application, RP# is controlled by the same RESET#
signal that resets the system CPU.
internal circuits. RP# must be held low for a minimum 01
down until inittal memory access outputs are valid. After
CUI is reset to read array mode and status register is set tc
During block erase or word/byte
will abort the operation. RY/BY#
reset operation is complete. Memory
altered are no longer valid; the data may be partially
erased or written. Time tpHwL is required after RP# goes
to logic-high
written.
flash memories provide status information when accessed
impedance state independent of OE#. If deselected during
block
functioning,
operation completes.
3.4 Deep Power-Down
RP# at V,, initiates the deep power-down
In read modes, RP#-low
output drivers in a high-impedance state and turns off all
this wake-up interval, normal operation is restored. The
80H.
With OE# at a logic-high level (V&,
are disabled. Output pins (DQu-DQ,s)
high-impedance state.
3.3 Standby
CE# at a logic-high level (V,,)
standby mode which substantially reduces device power
consumption. DQ,-DQ,,
100 ns. Time tpHQv is required after return from power-
3.2 Output Disable
erase or word/byte
and consuming
(V,,)
before another command can be
outputs are placed in a high.
deselects the memory, places
write,
active power
write modes, RP#-low
remains low until the
the device continue:
places the device ir
the device output!
mode.
are placed in i
contents being
until the
Rev. 1.1
8