CY7C0430BV-133BGC Cypress Semiconductor Corp, CY7C0430BV-133BGC Datasheet
CY7C0430BV-133BGC
Specifications of CY7C0430BV-133BGC
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CY7C0430BV-133BGC Summary of contents
Page 1
... Dual Chip Enables on all ports for easy depth expansion • Separate upper-byte and lower-byte controls on all ports • Simple array partitioning (CY7C0430BV only) — Internal mask register controls counter wrap-around — Counter-Interrupt flags to indicate wrap-around — Counter and mask registers readback on address • ...
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... One cycle is required with chip enables asserted to reactivate the outputs. The CY7C0430BV (64K × 18 device) is the only member of the family which contains burst contains for simple array parti- tioning. Counter enable inputs are provided to stall the ...
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... Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks. 4. Counter functionality applies only to CY7C0430BV (64K × 18) device option. These pins are either GND or NC for CY7C04312BV and CY7C04314BV. Document #: 38-06027 Rev. *A The counter and mask register operations are described in more details in the following sections ...
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... Document #: 38-06027 Rev Port-1 I/O Control 9 Addr. Read Port 1 Readback Register Port 1 Mask Register Port 1 Address Port 1 Decode Counter/ Address Register Port 1 R/W P1 Interrupt CE 0P1 CE Logic 1P1 OE P1 CLK P1 MRST CY7C0430BV CY7C04312BV CY7C04314BV 16K/32K/64K × 18 QuadPort DSE Array INT P1 Page [+] Feedback ...
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... VSS VSS VDD VDD2 VSS2 VSS2 I/ I/O0 VSS2 P2 P3 I/O8 I/O4 I/O2 MRST CLKBIST I/O2 I/ 1/O7 I/O5 I/O3 I/O1 I/O1 I/O3 I/ CY7C0430BV CY7C04312BV CY7C04314BV I/O16 I/O9 I/O11 I/O13 I/O15 I/O17 I/O17 I/O10 I/O12 I/O14 I/O16 UB VDD1 VSS2 I/O15 R/W CE0 CE1 ...
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... CNTINC Counter Increment Input. Asserting this signal LOW P3 P4 increments the burst address counter of its respective port on each rising edge of CLK. CY7C0430BV CY7C04312BV CY7C04314BV CY7C04312BV -133 -100 Unit [1] 133 100 MHz 4 ...
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... JTAG TAP. BIST Clock Input. Thermal Ground for Heat Dissipation. Ground Input. Power Input. Address Lines Ground Input. Address Lines Power Input. Data Lines Ground Input. Data Lines Power Input. CY7C0430BV CY7C04312BV CY7C04314BV Description = LOW HIGH), the 0 1 from ...
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... Over the Operating Range Test Conditions GND Test Conditions MHz 3.3V CC CY7C0430BV CY7C04312BV CY7C04314BV Ambient Temperature +70 C 3.3V 150 mV – +85 C 3.3V 150 mV CY7C043XXBV -100 Max. Min. Typ. Max. Unit 2.4 0.4 0.4 2.0 0.8 0.8 10 –10 10 700 ...
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... AC Test Load OUTPUT 1.5V TH (a) Normal Load 1.5V 50 TDO Z = GND (c) TAP Load Note: 10. Test conditions pF. Document #: 38-06027 Rev OUTPUT OUTPUT (b) Three-State Delay 3.0V 90% 90% 10% 10% GND t R All Input Pulses CY7C0430BV CY7C04312BV CY7C04314BV = 1. Page [+] Feedback ...
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... MHz. t Min. for commercial is 7.4 ns. MAX2 CYC2 13. This parameter is guaranteed by design, but it is not production tested. 14. Valid for both address and data outputs. Document #: 38-06027 Rev. *A CY7C0430BV CY7C04312BV CY7C04314BV [11] CY7C04312BV -133 -100 Min. Max. ...
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... TDI Hold after TCK Clock Rise TDIH t TCK Clock Low to TDO Valid TDOV t TCK Clock Low to TDO Invalid TDOX f Maximum CLKBIST Frequency BIST t CLKBIST High Time BH t CLKBIST Low Time BL Document #: 38-06027 Rev. *A CY7C0430BV CY7C04312BV CY7C04314BV [11] CY7C04312BV -133 -100 Min. Max. Min. Max 7.5 1 ...
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... S 16. To Reset the test port without resetting the device, TMS must be held low for five clock cycles. Document #: 38-06027 Rev TMSH t TMSS t t TDIS TDIH t TDOX t TDOV t CYC2 t CL2 RSR ACTIVE CY7C0430BV CY7C04312BV CY7C04314BV t TCYC Page [+] Feedback ...
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... Addresses do not have to be accessed sequentially. Note 18 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference only. 21 internal signal VIL and Document #: 38-06027 Rev CL2 A A n+1 n+2 t CD2 CKLZ . IH following the next rising edge of the clock CY7C0430BV CY7C04312BV CY7C04314BV n n+1 n+2 t OHZ t OLZ t OE Page [+] Feedback ...
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... CKLZ n+1 n CD2 CKHZ Q n Read No Operation . constantly loads the address on the rising edge of the CLK; numbers are for reference only. IL CY7C0430BV CY7C04312BV CY7C04314BV CD2 CKHZ CKHZ CKLZ CD2 CKHZ CD2 CKLZ A A n+3 n+4 t CD2 t CKLZ Write Read ...
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... Document #: 38-06027 Rev. *A [24, 25, 26, 27 n+1 n+2 n n+2 n+3 t CD2 OHZ Read Write [28, 29 SCINC HCINC t CD2 n+1 DC Counter Hold Read with Counter . CY7C0430BV CY7C04312BV CY7C04314BV A A n+4 n+5 t CD2 Q n+4 t CKLZ Read Q Q n+2 n+3 Read with Counter Page [+] Feedback ...
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... SD HD Write External Address Notes CNTRST = MRST = MKLD = MKRD = CNTRD = 31. Counter operation is only available on the CY7C0430BV. The CY7C04312BV and CY7C04314BV do not support the counter functions. Document #: 38-06027 Rev. *A [29, 30, 31 n+1 n+1 n+2 Write with Write Counter Counter Hold IH. ...
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... DATA OUT Counter Reset Notes: 32 MRST = MKLD = MKRD = CNTRD = 33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06027 Rev Write Read Address 0 Address 0 Address CY7C0430BV CY7C04312BV CY7C04314BV n n HCLD SCLD A n Read ...
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... This is the value of the address counter being read out on the address lines. Document #: 38-06027 Rev HCINC t SCRD A A n+1 n CD2 n+1 Read Data with Counter . IH in next clock cycle. CKLZ . CKHZ CY7C0430BV CY7C04312BV CY7C04314BV Note 35 Note 36 t CA2 t t CKHZ CKLZ [37] A n+2 t HCRD A A n+2 n CKLZ CKHZ Q Q ...
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... CE = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC = 39. This is the value of the Mask Register read out on the address lines. Document #: 38-06027 Rev. *A Note 35 t CKLZ t t SMRD HMRD Read Mask Register Value . IH CY7C0430BV CY7C04312BV CY7C04314BV Note 36 t CA2 t CKHZ A [39 Page [+] Feedback ...
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... Port 2 will read the most recent data (written by Port 1) (t CCS Document #: 38-06027 Rev CKLZ t CCS CD2 t DC CYC2 CY7C0430BV CY7C04312BV CY7C04314BV violated, indeterminate CCS + t ) after the rising edge of Port 2’s clock. If CYC2 CD2 + t ) after the rising edge of Port 2’s clock. CD2 Page [+] Feedback ...
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... Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock. Document #: 38-06027 Rev HCLD t t HCINC SCINC xx7Dh xx7Eh SINT t RINT t HA FFFE A m CY7C0430BV CY7C04312BV CY7C04314BV xx7Fh xx00h xx00h t t SCINT RCINT A A n+2 n m+3 m Page [+] Feedback ...
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... Load of Address Lines into Mask Register Load Load of Address Lines into Counter/Address Register Increment Counter Increment Readback Readback Counter on Address Lines Readback Readback Mask Register on Address Lines Hold Counter Hold CY7C0430BV CY7C04312BV CY7C04314BV Operation Deselected Deselected Write Read Outputs Disabled [31, 51, 54, 55] Operation Page [+] Feedback ...
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... Counter Read signal (CNTRD) and Mask Register Read signal (MKRD). Both signals are synchronized to the port's clock as shown in Table 2. Counter read has a higher priority than mask read. CY7C0430BV CY7C04312BV CY7C04314BV flag, a write by P1 LOW ...
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... FFFF. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of XXX8. The “blocked” addresses (in this case, the 6th address through CY7C0430BV CY7C04312BV CY7C04314BV Memory Array ...
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... The counter and mask register operations are totally independent of port chip enables. IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) The CY7C0430BV incorporates a serial boundary scan test access port (TAP). This port is fully compatible with IEEE Standard 1149.1-2001 standard 3.3V I/O logic levels composed of three input connections and one output connection required by the test logic defined by the standard ...
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... Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the QuadPort DSE device signal must be stabilized long enough to meet the TAP controller’s CY7C0430BV CY7C04312BV CY7C04314BV instructions loaded ...
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... JTAG interface. An MBIST Result Register (MRR) will be used to store the pass-fail results. The MRR is a 25-bit register that will be Document #: 38-06027 Rev. *A CY7C0430BV CY7C04312BV CY7C04314BV connected between TDI and TDO during the internal scan (INT_SCAN) operation. The MRR will contain the total number of fail read cycles of the entire MBIST sequence. MRR[0] (bit 0) is the Pass/Fail bit. A “ ...
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... Bidirectional signals (address lines, datalines) require two cells so that one (the odd cell) is used to control a three-state buffer. Input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout. CY7C0430BV CY7C04312BV CY7C04314BV 62 P1_IO(17-9) ...
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... The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-06027 Rev. *A [59] 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C0430BV CY7C04312BV CY7C04314BV 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... MBIST Debug Register (MDR) 391 0 Boundary Scan Register (BSR) TAP CONTROLLER Value Reserved for version number Defines Cypress part number Allows unique identification of QuadPort DSE device vendor Indicate the presence register CY7C0430BV CY7C04312BV CY7C04314BV Selection TDO Circuitry (MUX) TCK TMS MRST Description ...
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... Up count from 0 to 64K. All ports read 1s, then Port 1 writes 0s, then all ports read 0s (MIA_r1w0r0). Down count from 64K to 0. MIA_r0w1r1. Down count MIA_r1w0r0. Read all 0s. Port 1 write all zeros to memory using March2 Algorithm (M2A). Up count M2A_r0w1r1. Up count M2A_r1w0r0. Down count M2A_r0w1r1. CY7C0430BV CY7C04312BV CY7C04314BV Page [+] Feedback ...
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... A7_P4 Debug 18 A8_P4 Reserved 20 A9_P4 Reserved 22 A10_P4 24 A11_P4 26 A12_P4 Bump (Ball A13_P4 30 A14_P4 32 A15_P4 34 CNTINT_P4 36 CNTRST_P4 38 MKLD_P4 40 CNTLD_P4 CY7C0430BV CY7C04312BV CY7C04314BV Description Signal Name Bump (Ball) ID F20 F19 F18 E20 E19 D19 D18 C20 C19 F17 K18 H18 H17 Page [+] Feedback ...
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... IO3_P2 188 IO4_P2 190 IO5_P2 192 IO6_P2 194 IO7_P2 196 IO8_P2 198 A0_P2 200 A1_P2 202 A2_P2 204 A3_P2 CY7C0430BV CY7C04312BV CY7C04314BV Signal Name Bump (Ball) ID M17 Y15 W15 Y16 W16 Y17 W17 Y18 W18 Y19 V12 Y11 W12 Y12 W13 ...
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... IO16_P2 338 IO17_P2 340 IO9_P1 342 IO10_P1 344 IO11_P1 346 IO12_P1 348 IO13_P1 350 IO14_P1 352 IO15_P1 354 IO16_P1 356 IO17_P1 358 IO9_P3 360 IO10_P3 362 IO11_P3 364 IO12_P3 366 IO13_P3 368 IO14_P3 CY7C0430BV CY7C04312BV CY7C04314BV Signal Name Bump (Ball A10 ...
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... IO16_P4 A14 392 IO17_P4 B14 Ordering Information 10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K × 18) Speed (MHz) Ordering Code 133 CY7C0430BV-133BGC CY7C0430BV-133BGI 100 CY7C0430BV-100BGC CY7C0430BV-100BGI 10 Gb/s 3.3V QuadPort DSE Family 1/2 Mb (32K x 18) Speed (MHz) Ordering Code 133 CY7C04312BV-133BGC 100 CY7C04312BV-100BGC 10 Gb/s 3 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C0430BV CY7C04312BV ...
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... Document #: 38-06027 Rev. *A Description of Change SZV Change from Spec number: 38-01052 to 38-06027 FSG Remove Preliminary, TM from DSE. Change RUNBIST to CYBIST. Updated ISB values. Added notes 9 and 14. Increased commercial prime bin to 135 MHz. CY7C0430BV CY7C04312BV CY7C04314BV Page [+] Feedback ...