CY7C0430BV-133BGC Cypress Semiconductor Corp, CY7C0430BV-133BGC Datasheet - Page 6

• Manufacturer Part Number: CY7C0430BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0430BV-133BGC

• Density: 1.125Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 750mA
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 272
• Word Size: 18b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06027 Rev. *A
Selection Guide
Pin Definitions
f
Max Access Time (Clock to Data)
Max Operating Current I
Max Standby Current for I
Max Standby Current for I
A
I/O
CLK
LB
UB
CE
OE
R/W
MRST
CNTRST
MKLD
CNTLD
CNTINC
MAX2
0P1
P1
0P1
P1
0P1
P1
Port 1
P1
P1
–A
–I/O
,CE
P1
15P1
P1
[6]
P1
P1
[6]
1P1
17P1
[6]
[6]
A
I/O
CLK
LB
UB
CE
OE
R/W
CNTRST
MKLD
CNTLD
CNTINC
0P2
P2
0P2
P2
0P2
P2
Port 2
P2
P2
–A
–I/O
,CE
P2
CC
15P2
P2
SB1
SB3
[6]
P2
P2
[6]
1P2
17P2
[6]
[6]
(All ports TTL Level)
(All ports CMOS Level)
A
I/O
CLK
LB
UB
CE
OE
R/W
CNTRST
MKLD
CNTLD
CNTINC
0P3
P3
0P3
P3
0P3
P3
Port 3
P3
P3
–A
–I/O
P3
,CE
15P3
P3
[6]
P3
P3
[6]
1P3
17P3
[6]
[6]
A
I/O
CLK
LB
UB
CE
OE
R/W
CNTRST
MKLD
CNTLD
CNTINC
0P4
P4
0P4
P4
0P4
P4
Port 4
P4
P4
–A
–I/O
,CE
P4
15P4
P4
[6]
P4
P4
[6]
1P4
17P4
[6]
[6]
Address Input/Output.
Data Bus Input/Output.
Clock Input. This input can be free running or strobed.
Maximum clock input rate is f
Lower Byte Select Input. Asserting this signal LOW
enables read and write operations to the lower byte. For
read operations both the LB and OE signals must be
asserted to drive output data on the lower byte of the data
pins.
Upper Byte Select Input. Same function as LB, but to
the upper byte.
Chip Enable Input. To select any port, both CE
CE
and CE
Output Enable Input. This signal must be asserted LOW
to enable the I/O data lines during read operations. OE
is asynchronous input.
Read/Write Enable Input. This signal is asserted LOW
to write to the dual port memory array. For read opera-
tions, assert this pin HIGH.
Master Reset Input. This is one signal for All Ports.
MRST is an asynchronous input. Asserting MRST LOW
performs all of the reset functions as described in the text.
A MRST operation is required at power-up.
Counter Reset Input. Asserting this signal LOW resets
the burst address counter of its respective port to zero.
CNTRST is second to MRST in priority with respect to
counter and mask register operations.
Mask Register Load Input. Asserting this signal LOW
loads the mask register with the external address
available on the address lines. MKLD operation has
higher priority over CNTLD operation.
Counter Load Input. Asserting this signal LOW loads
the burst counter with the external address present on
the address pins.
Counter Increment Input. Asserting this signal LOW
increments the burst address counter of its respective
port on each rising edge of CLK.
1
must be asserted to their active states (CE
CY7C04312BV
1
V
133
-133
IH
750
200
4.2
15
).
[1]
Description
CY7C04312BV
MAX
CY7C04312BV
CY7C04314BV
.
-100
100
600
150
CY7C0430BV
5.0
15
Page 6 of 37
0
0
AND
Unit
MHz
mA
mA
mA
ns
V
IL
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