CY7C0430BV-133BGC Cypress Semiconductor Corp, CY7C0430BV-133BGC Datasheet - Page 28

• Manufacturer Part Number: CY7C0430BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0430BV-133BGC

• Density: 1.125Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 750mA
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 272
• Word Size: 18b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06027 Rev. *A
Figure 3 is a representation of the 100-bit MDR packet. The
packet follows a two-bit header that has a logic “1” value, and
represents two TCK cycles. MDR[97:26] represent the BIST
comparator values of all four ports (each port has 18 data
lines). A value of “1” indicates a bit failure. The scanned out
data is from LSB to MSB. MDR[25:10] represent the failing
address (MSB to LSB). The state of the BIST controller is
scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A “0”
in bit 2 means test not complete. The user has to monitor this
bit at every packet to determine if more failure packets need
to be scanned out at the end of the BIST operations. If the
value is “0” then BIST must be repeated to capture the next
failing packet. If it is “1,” it means that the last failing packets
have been scanned out. A trailer similar to the header repre-
sents the end of a packet.
MCR_SCAN
This instruction will connect the Memory BIST Control
Register (MCR) between TDI and TDO. The default value
99
25
2
P4_IO(17-9)
3
61
TD
1
P4_IO(8-0)
9
P/F
97
A(15-0)
1
MBIST_State
1
1
1
98
0
10
Figure 3. MBIST Debug Register Packet
P3_IO(17-9)
P3_IO(8-0)
4
P2_IO(17-9)
P2_IO(8-0)
(upon master reset) is “00.” Shift_DR state will allow modifying
the MCR to extend the MBIST functionality.
MBIST Control States
Thirty-five states are listed in Table 7. Four data algorithms are
used in debug mode: moving inversion (MIA), march_2 (M2A),
checkerboard (CBA), and unique address algorithm (UAA).
Only Port 1 can write MIA, M2A, and CBA data to the memory.
All four ports can read any algorithm data from the QuadPort
DSE device memory. Ports 2, 3, and 4 will only write UAA data.
Boundary Scan Cells (BSC)
Table 9 lists all QuadPort DSE family I/Os with their associated
BSC. Note that the cells have even numbers. Every I/O has
two boundary scan cells. Bidirectional signals (address lines,
datalines) require two cells so that one (the odd cell) is used
to control a three-state buffer. Input only and output only
signals have an extra dummy cell (odd cells) that are used to
ease device layout.
P1_IO(17-9)
P1_IO(8-0)
62
26
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