CY7C0430BV-133BGC Cypress Semiconductor Corp, CY7C0430BV-133BGC Datasheet - Page 2

• Manufacturer Part Number: CY7C0430BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0430BV-133BGC

• Density: 1.125Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 750mA
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 272
• Word Size: 18b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06027 Rev. *A
Functional Description
The CY7C043XXBV is a family of 10 Gb/s, true four-ported
Datapath Switching Elements with port speeds of up to
133 MHz
(64K ×18), ½-Mb (32K x18), and ¼-Mb (16K × 18) options. All
four ports may be clocked at independent frequencies from
one another. Simultaneous reads are allowed for accesses to
the same address location; however, simultaneous reading
and writing to the same address is not allowed. Any port can
write to a certain location while other ports are reading that
location simultaneously, if the timing spec for port to port delay
(t
than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
t
CD2
CCS
= 4.2 ns. Each port contains a burst counter on the input
) is met. The result of writing to the same location by more
[1]
. The members of the family include 1-Mb
Pre-processed DATA Path
PORT 1
PORT 2
PORT 1
PORT 2
PORT 3
DATA CLASSIFICATION ENGINE
PARALLEL PACKET PROCESSING
DATA PATH AGGREGATOR
DATA PATH MANAGER FOR
QuadPort
DSE Family
Processor 1
Processor 2
Queue #1
Queue #2
address register. After externally loading the counter with the
initial address the counter will self-increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430BV (64K × 18 device) is the only member of
the family which contains burst contains for simple array parti-
tioning. Counter enable inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast interleaved memory
Processed DATA Path
0
or LOW on CE
PORT 4
PORT 3
PORT 4
1
for one clock cycle will power
CY7C04312BV
CY7C04314BV
CY7C0430BV
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