CY7C0430BV-133BGC Cypress Semiconductor Corp, CY7C0430BV-133BGC Datasheet - Page 22

• Manufacturer Part Number: CY7C0430BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0430BV-133BGC

• Density: 1.125Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 750mA
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 272
• Word Size: 18b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06027 Rev. *A
Table 1. Read/Write and Enable Operation (Any Port)
Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)
Notes:
CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD
51. “X” = “Don’t Care,” “H” = V
52. OE is an asynchronous input signal.
53. When CE changes state, deselection and read happen after one cycle of latency.
54. CE
55. Counter operation and mask register operation are independent of Chip Enables.
X
OE
X
X
X
H
L
0
= OE = V
H
H
H
H
H
H
H
L
IL
CLK
; CE
X
H
H
H
H
H
H
X
L
1
= R/W = V
IH
, “L” = V
X
X
H
H
H
H
H
L
Inputs
IH
CE
.
H
X
L
L
L
IL
0
.
X
X
X
H
H
H
H
L
CE
H
H
H
X
L
X
X
X
X
H
H
H
1
L
R/W
X
X
X
X
X
H
H
[51, 52, 53]
L
X
X
H
X
L
X
X
X
X
X
X
H
L
Increment Counter Increment
Readback Readback Counter on Address Lines
Readback Readback Mask Register on Address Lines
I/O
Outputs
Master-
Mode
Reset
Reset
High-Z
High-Z
High-Z
Load
Load
Hold
D
0
D
OUT
–I/O
IN
17
Counter/Address Register Reset and Mask
Register Set (resets entire chip as per reset
state table)
Counter/Address Register Reset
Load of Address Lines into Mask Register
Load of Address Lines into Counter/Address
Register
Counter Hold
[31, 51, 54, 55]
Deselected
Deselected
Write
Read
Outputs Disabled
Operation
CY7C04312BV
CY7C04314BV
Operation
CY7C0430BV
Page 22 of 37
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