CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 100

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

11.2
Figure 11-2 shows how to cascade up to four blocks. Each block contains up to eight CYNSE70064A devices except the last,
and the interconnection within each was shown in the previous subsection with the cascading of up to eight devices in a block.
Note. The interconnection between blocks for depth-cascading is important. The BHO signals of a device is connected to the
BHI signal of the devices in all the downstream blocks. The BHO signal being input into a block must be connected to BHI signal
of all the devices in the block. The order in which BHO signal of a block is connected to BHI signals of other devices in downstream
blocks is not important. For each successful Search, a block asserts BHO[2], BHO[1], and BHO[0]. The BHO[2:0] signals for a
block are the signals taken only from the last device in the block. For all other devices within that block, these signals stay open
and floating. The delay from the time search command is input into the device to the time BHO is asserted is constant, that is 5
clock cycles. Any device that receives an asserted BHI signal gives up its claim to drive read and write accesses to the SRAM.The
host ASIC must program the table size (TLSZ) field to 10 in each of the devices for cascading up to 31 devices (in up to four
blocks) to provide the necessary latency for the driver of SRAM signals to be chosen..
11.3
Bit[0] of each of the 68-bit entries is designated as a special bit (1 = occupied; 0 = empty). For each Learn or PIO Write to the
data array, each device asserts FULO[1] and FULO[0] if it does not have any empty locations within it (see Figure 11-3). Each
device combines the FULO signals from the devices above it with its own full status to generate a FULL signal that gives the full
status of the table up to the device asserting the FULL signal. Figure 11-3 shows the hardware connection diagram for generating
the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL signal from the last device
should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the other devices should be left
open. Note. The Learn instruction is supported for only up to eight devices, whereas FULL cascading is allowed only for one
block in tables containing more than eight devices. In tables for which a Learn instruction is not going to be used, the bit[0] of
each 68-bit entry should always be set to 1.
Document #: 38-02041 Rev. *F
Depth-Cascading up to 31 Devices (Four Blocks)
Depth-Cascading for a FULL Signal
SSF, SSV
DQ[67:0]
CMD[8:0], CMDV
Figure 11-2. Depth-Cascading Four Blocks
Block of 8 CYNSE70064As Block 2 (devices 16–23)
Block of 7 CYNSE70064As Block 3 (devices 24-30)
Block of 8 CYNSE70064As Block 1 (devices 8–15)
Block of 8 CYNSE70064As Block 0 (devices 0–7)
BHO[2]
BHO[2]
BHI[2]
BHO[2]
BHO[2]
BHI[2]
BHI[2]
BHI[2]
BHO[1]
BHO[1]
BHI[1]
BHO[1]
BHO[1]
BHI[1]
BHI[1]
BHI[1]
BHO[0]
BHO[0]
BHO[0]
BHO[0]
BHI[0]
BHI[0]
BHI[0]
BHI[0]
GND
GND
GND
SRAM
CYNSE70064A
Page 100 of 128