CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 31

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Note. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B, and the even
and odd pairs of GMRs selected for the comparison must be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 10-12. The entire table with eight devices of 68-bit entries is compared to
a 68-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The
effective GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and
selected by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the
command) is also stored in both even and odd comparand register pairs (selected by the Comparand Register Index in command
cycle B) in each of the eight devices. In the ×68 configuration, only the even comparand register can subsequently be used by
the Learn command in one of the devices (only the first non-full device). The word K (presented on the DQ bus in both cycles A
and B of the command) is compared with each entry in the table starting at location 0. The first matching entry’s location address
L is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on
page 101). The global winning device will drive the bus in a specific cycle. On a global miss cycle the device with LRAM = 1
(default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the default driver
for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-13.
Table 10-13. The Latency of Search from Instruction to SRAM Access Cycle
The latency of the Search from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ = 01). SSV and
SSF also shift further to the right for different values of HLAT, as specified in Table 10-14.
Table 10-14. Shift of SSF and SSV from SADR
Document #: 38-02041 Rev. *F
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
000
001
010
100
101
011
Must be same in each of the eight
Will be same in each of the eight
Comparand Register (Odd)
Comparand Register (Even)
67
devices
devices
K
K
Figure 10-12. x68 Table with Eight Devices
0
Max Table Size
256K × 68 bits
992K × 68 bits
32K × 68 bits
Location
address
262143
L
0
1
2
3
67
67
(68-bit configuration)
CFG = 00000000
Number of CLK Cycles
GMR
K
0
1
2
3
4
5
0
0
Latency in CLK Cycles
(First matching entry)
4
5
6
CYNSE70064A
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