CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 110

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.7
The following explains the SRAM Write operation done through a table(s) of up to eight devices with the following parameters
(TLSZ = 01). The diagram of such a table is shown in Figure 12-9. The following assumes that SRAM access is done through
CYNSE70064A device number 0. Figure 12-10 and Figure 12-11 show the timing diagram for device number 0 and device
number 7, respectively.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM
bus with the same latency as that of a Search instruction as measured from the second cycle of the Write command.
Document #: 38-02041 Rev. *F
• Cycle 1A: The host ASIC applies the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle. Note. CMD[2] must be set to 0 for SRAM
Write, as burst Writes into the SRAM are not supported.
address with DQ[20:19] set to 10 to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write, as burst Writes
into the SRAM are not supported.
SRAM Write with a Table of up to Eight Devices
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1.
CMD[8:2]
CLK2X
CMD[1:0]
PHS_L
CMDV
SADR
OE_L
CE_L
ALE_L
WE_L
SSV
Figure 12-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
SSF
ACK
DQ
0
z
0
1
z
0
1
1
cycle
1
Address
Write
A
B
cycle
2
x
cycle
3
x
x
cycle
4
cycle
1
5
Address
cycle
6
0
0
0
CYNSE70064A
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