CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 7

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CYNSE70064A
LIST OF TABLES
Table 5-1. CYNSE70064A Signal Description ..................................................................................... 11
Table 7-1. Register Overview ............................................................................................................... 13
Table 7-2. Search Successful Register Description .............................................................................14
Table 7-3. Command Register Description ........................................................................................... 15
Table 7-4. Information Register Description ......................................................................................... 16
Table 7-5. Read Burst Register Description ......................................................................................... 16
Table 7-6. Write Burst Register Description ......................................................................................... 16
Table 7-7. NFA Register ....................................................................................................................... 17
Table 8-1. Bit Position Match ................................................................................................................ 17
Table 10-1. Command Codes ............................................................................................................... 18
Table 10-2. Command Parameters ...................................................................................................... 19
Table 10-3. Read Command Parameters ............................................................................................. 19
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM ........................................... 20
Table 10-5. Read Address Format for Internal Registers ..................................................................... 20
Table 10-6. Read Address Format for Data and Mask Arrays .............................................................. 21
Table 10-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write) ..................... 22
Table 10-8. Write Address Format for Internal Registers ..................................................................... 22
Table 10-9. Write Address Format for Data and Mask Array (Burst Write) .......................................... 23
Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 26
Table 10-11. Shift of SSF and SSV from SADR ................................................................................... 26
Table 10-12. Hit/Miss Assumption ........................................................................................................ 27
Table 10-13. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 31
Table 10-14. Shift of SSF and SSV from SADR ................................................................................... 31
Table 10-15. Hit/Miss Assumptions ...................................................................................................... 32
Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 46
Table 10-17. Shift of SSF and SSV from SADR ................................................................................... 46
Table 10-18. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 48
Table 10-19. Shift of SSF and SSV from SADR ................................................................................... 48
Table 10-20. Hit/Miss Assumption ........................................................................................................ 49
Table 10-21. Search Latency from Instruction to SRAM Access Cycle ................................................ 54
Table 10-22. Shift of SSF and SSV from SADR ................................................................................... 54
Table 10-23. Hit/Miss Assumption ........................................................................................................ 55
Table 10-24. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 69
Table 10-25. Shift of SSF and SSV from SADR ................................................................................... 69
Table 10-26. The Latency of Search from C and D Cycles to SRAM Access Cycle ............................ 71
Table 10-27. Shift of SSF and SSV from SADR ................................................................................... 71
Table 10-28. Hit/Miss Assumption ........................................................................................................ 72
Table 10-29. The Latency of Search from C and D cycles to SRAM Access Cycle ............................. 77
Table 10-30. Shift of SSF and SSV from SADR ................................................................................... 77
Table 10-31. Hit/Miss Assumption ........................................................................................................ 78
Table 10-32. The Latency of Search from C and D cycles to SRAM Access Cycle ............................. 92
Table 10-33. Shift of SSF and SSV from SADR ................................................................................... 92
Table 10-34. The Latency of SRAM Write Cycle from Second Cycle of Learn Instruction ................... 97
Table 12-1. SRAM Bus Address ......................................................................................................... 102
Table 12-2. Required Idle Cycles Between Commands ..................................................................... 117
Table 15-1. Supported Operations ..................................................................................................... 118
Table 16-1. DC Electrical Characteristics for CYNSE70064A ............................................................ 119
Table 16-2. Operating Conditions for CYNSE70064A ........................................................................ 119
Table 15-2. TAP Device ID Register .................................................................................................. 119
Table 17-1. AC Timing Parameters with CLK2X ................................................................................ 120
Document #: 38-02041 Rev. *F
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