CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 103

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.4
The following explains the SRAM Read operation completed through a table of up to eight devices using the following parameters:
TLSZ = 01. Figure 12-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved
through CYNSE70064A device number 0. Figure 12-3 and Figure 12-4 show timing diagrams for device number 0 and device
number 7, respectively.
At the end of cycle 7, the selected device floats ACK in three-state condition and a new command can begin.
Document #: 38-02041 Rev. *F
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0].
• Cycle 5: The selected device continues to drive DQ[67:0] and drives ACK from High-Z to LOW.
• Cycle 6: The selected device drives the Read address on SADR[21:0]. It also drives ACK HIGH, CE_L LOW, WE_L HIGH,
• Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and DQ bus in a three-state condition. It continues to drive ACK LOW.
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. During this cycle the host ASIC also supplies SADR[21:20] on CMD[8:7].
address, with DQ[20:19] set to 10 to select the SRAM address.
and ALE_L LOW.
SRAM Read with a Table of up to Eight Devices
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1
CMD[8:2]
CMD[1:0]
Figure 12-1. SRAM Read Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
CLK2X
CMDV
ALE_L
PHS_L
SADR
SSV
WE_L
SSF
OE_L
CE_L
ACK
DQ
0
z
0
1
z
0
1
1
cycle
1
Address
A
Read
B
cycle
2
z
cycle
3
cycle
4
DQ driven by CYNSE70064A
0
cycle
Address
5
0
0
1
cycle
1
1
6
z
z
0
CYNSE70064A
z
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