CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 71

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Note. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR index in cycle A selects a pair of GMRs that apply to DQ data in cycles A and B. The GMR index in cycle C selects a
pair of GMRs that apply to DQ data in cycles C and D.
The logical 272-bit Search operation is shown in Figure 10-51. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C. The 272-bit
word K that is presented on the DQ bus in cycles A, B, C and D of the command is compared with each entry in the table starting
at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM address on
SADR[21:0] lines (See “SRAM Addressing” on page 101.). Note. The matching address is always going to be location 0 in a
four-entry page for a 272-bit Search (two LSBs of the matching index will be 00).
The Search command is a pipelined operation and executes at one-fourth the rate of the frequency of CLK2X for 272-bit searches
in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search command
(measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-26.
Table 10-26. The Latency of Search from C and D Cycles to SRAM Access Cycle
The latency of a Search from command to SRAM access cycle is 4 for only a single device in the table and TLSZ = 00. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-27.
Table 10-27. Shift of SSF and SSV from SADR
Document #: 38-02041 Rev. *F
• Cycle B: The host ASIC continues to drive the CMDV HIGH and continues to apply the command code of Search command
• Cycle C: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
• Cycle D: The host ASIC continues to drive the CMDV HIGH and applies Search command code (10) on CMD[1:0]. CMD[8:6]
(10) on CMD[1:0]. The DQ[67:0] is driven with the 68-bit data ([204:136]) to be compared to all locations 1 in the four 68-bits-word
page.
signals must be driven with the index to the GMR pair used for bits [135:0] of the data being searched. CMD[8:7] signals must
be driven with the bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit
data ([135:68]) to be compared to all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag
(see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations
3 in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x272 tables.
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
000
001
010
100
101
011
110
111
Location
address
32764
GMR
12
L
0
4
8
K
271
271
Figure 10-51. ×272 Table with One Device
0
Max Table Size
248K × 272 bits
CFG = 10101010
A
64K × 272 bits
8K × 272 bits
1
B
(272-bit configuration)
2
C
Number of CLK Cycles
3
D
0
1
2
3
4
5
6
7
0
Latency in CLK Cycles
0
4
5
6
(First matching entry)
CYNSE70064A
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