CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 92

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The logical 272-bit Search operation is as shown in Figure 10-70. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C in each of the
31 devices. The 272-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to each
entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part
of the SRAM address on the SADR[21:0] lines (See “SRAM Addressing” on page 101.). Note. The matching address is always
going to be location 0 in a four-entry page for 272-bit Search (two LSBs of the matching index will be 00).
The Search command is a pipelined operation and executes a Search at one-fourth the rate of the frequency of CLK2X for 272-bit
searches in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search
command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-32.
Table 10-32. The Latency of Search from C and D cycles to SRAM Access Cycle
The latency of a Search from command to SRAM access cycle is 6 for only a single device in the table and TLSZ = 10. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-33.
Table 10-33. Shift of SSF and SSV from SADR
10.15
This subsection will cover mixed searches (×68, ×136, and ×272) with tables of different widths (×68, ×136, ×272). The sample
operation shown is for a single device with CFG = 10010000 containing three tables of ×68, ×136, and ×272 widths. The operation
can be generalized to a block of eight to 31 devices using four blocks; the timing and the pipeline operation is the same as
described previously for fixed searches on a table of one-width-size.
Figure 10-71 shows three sequential searches: first, a 68-bit Search on the table configured as ×68, then a 136-bit Search on a
table configured as ×136, and finally a 272-bit Search on the table configured as ×272 bits that each results in a hit. Note.In order
to differentiate between different partitions, table ID bits will have to be allocated. In the case of this example, 2 bits are needed
to differentiate between partitions of 3 different sizes. These could be any two bits. As an example, DQ[67:66] will be 00 in each
of the two A and B cycles of the ×68-bit Search (Search1). DQ[67:66] is 01 in each of the A and B cycles of the ×136-bit Search
Document #: 38-02041 Rev. *F
Mixed-Sized Searches on Tables Configured with Different Widths Using an CYNSE70064A Device
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
000
001
010
100
101
011
110
111
Location
1015804
address
GMR
12
L
0
4
8
Figure 10-70. ×272 Table with 31 Devices
K
271
271
0
CFG = 10101010
A
Max Table Size
248K × 272 bits
64K × 272 bits
8K × 272 bits
1
B
(272-bit configuration)
Number of CLK Cycles
2
C
0
1
2
3
4
5
6
7
3
D
0
0
Latency in CLK Cycles
(First matching entry)
CYNSE70064A
Must be same in each
4
5
6
of the 31 devices
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