CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 68

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
The following is the sequence of operation for a single 136-bit Search command (also refer to “Command and Command
Parameters,” Subsection 10.2 on page 19).
The logical 136-bit Search operation is as shown in the following Figure 10-48. The entire table of 31 devices (consisting of 136-bit
entries) is compared against a 136-bit word K that is presented on the DQ bus in cycles A and B of the command using the GMR
and local mask bits. The GMR is the 136-bit word specified by the even and odd global mask pair selected by the GMR Index in
the command’s cycle A.
Document #: 38-02041 Rev. *F
• Cycle A: The host ASIC drives the CMDV HIGH and applies Search command code (10) on CMD[1:0] signals. CMD[5:3]
• Cycle B: The host ASIC continues to drive the CMDV HIGH and to apply Search command code (10) on CMD[1:0]. CMD[5:2]
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:7] signals must be driven with
the bits that will be driven on SADR[21:20] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68])
in order to be compared against all even locations. The CMD[2] signal must be driven to logic 0.
must be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles
A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0])to be compared
against all odd locations.
Figure 10-47. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)
SADR[21:0]
CMD[8:2]
|(LHI[6:0])
PHS_L
CMD[1:0]
I(BHI[2:0])
LHO[1:0]
BHO[2:0]
CE_L
ALE_L
OE_L
CMDV
WE_L
CLK2X
SSV
DQ
SSF
0
0
0
1
0
0
0
0
0
0
cycle
Search1
A B A B A B A B
1
A B A B A B A B
01
D1
cycle
Search2
2
01
D2
cycle
Search3
3
01
D3
cycle
4
Search4
01
D4
cycle
5
cycle
6
cycle
7
Search1
(Hit on
some
device
above.)
cycle
8
z
z
z
z
Search2
(Hit on some
device above.)
cycle
9
z
z
Search3
(Hit on
some
device
above.)
cycle
10
1
0
Search4
(Global miss; this device
default driver.)
0
1
0
CYNSE70064A
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