M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 10

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

M50LPW040
Table 8. A/A Mux Bus Operations
Table 9. Manufacturer and Device Codes
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux)
Interface has a more traditional style interface.
The signals consist of a multiplexed address
signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional
signal, RP, can be used to reset the memory.
The Address/Address Multiplexed (A/A Mux)
Interface
Programming
programming. Only a subset of the features
available to the Low Pin Count (LPC) Interface are
available; these include all the Commands but
exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface
unprotected. It is not possible to protect any blocks
through this interface.
Bus Read. Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Then
Write Enable (W) and Interface Reset (RP) must
be High, V
order to perform a Bus Read operation. The Data
Inputs/Outputs will output the value, see Figure
12, A/A Mux Interface Read AC Waveforms, and
Table
Characteristics, for details of when the output
becomes valid.
10/36
Bus Read
Bus Write
Output Disable
Reset
Manufacturer Code
Device Code
Operation
Operation
24,
IH
is
is
, and Output Enable, G, Low, V
A/A
selected
included
equipment
Mux
V
IL
all
for
Interface
V
V
V
V
V
or V
G
G
IH
IH
IL
IL
IL
for
the
IH
use
faster
blocks
V
Read
by
IL
V
V
V
V
V
or V
W
W
IH
IH
IH
IH
IL
factory
Flash
IL
IH
are
, in
AC
V
V
V
V
V
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC. The data should be set up on
the Data Inputs/Outputs; Output Enable, G, and
Interface Reset, RP, must be High, V
Enable, W, must be Low, V
Outputs are latched on the rising edge of Write
Enable, W. See Figure 13, A/A Mux Interface
Write AC Waveforms, and Table 25, A/A Mux
Interface Write AC Characteristics, for details of
the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at V
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, V
held Low, V
during a Program or Erase operation, the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
up to t
COMMAND INTERFACE
All Bus Write operations to the memory are
interpreted
Commands consist of one or more sequential Bus
Write operations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table 11,
Commands. Refer to Table 11 in conjunction with
the text descriptions below.
RP
V
RP
IH
IH
IH
IH
IH
IL
PLRH
A18-A1
to abort a Program or Erase operation.
IL
V
V
V
Don’t Care
Don’t Care
Don’t Care
by
CC
IL
IL
for t
V
or V
PP
PLPH
the
PPH
. If RP is goes Low, V
V
A0
V
Command
IH
IL
IL
. The Data Inputs/
Data Output
IL
Data Input
DQ7-DQ0
. RP must be
DQ7-DQ0
IH
Hi-Z
Hi-Z
20h
26h
and Write
Interface.
IH
.
IL
,