M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 12

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

M50LPW040
Table 11. Commands
Note: X Don’t Care, PA Program Address, PD Program Data, A
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits. During the Chip Erase operation the
memory will only accept the Read Status Register
command. All other commands will be ignored.
Typical Chip Erase times are given in Table 12.
The Chip Erase command sets all of the bits in the
memory to ‘1’. See Figure 17, Chip Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Chip Erase command.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. Two Bus Write
12/36
Read Memory Array
Read Status Register
Read Electronic Signature
Program
Quadruple Byte Program
Chip Erase
Block Erase
Clear Status Register
Program/Erase Suspend
Program/Erase Resume
Invalid/Reserved
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until a Read Mem-
ory Array command is issued.
Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-
sued.
Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A
differing only for address bit A0 and A1. After this command read the Status Register until the command completes and another com-
mand is issued.
Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes
and another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved commands.
Command
1
1
1
1
2
2
5
2
2
1
1
1
1
1
1
1
1
Addr
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1st
Data
D0h
C0h
FFh
70h
90h
98h
40h
10h
30h
80h
20h
50h
B0h
00h
01h
60h
2Fh
1,2,3,4
Addr
BA
PA
PA
A
X
1
Consecutive Addresses, BA Any address in the Block.
2nd
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the block is protected then the Block Erase
operation will abort, the data in the block will not be
changed and the Status Register will output the
error.
Data
D0h
10h
PD
PD
PD
Bus Write Operations
Addr
A
2
3rd
1
, A
Data
PD
2
, A
3
and A
Addr
A
3
4
must be consecutive addresses
4th
Data
PD
Addr
A
4
5th
Data
PD