M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 14

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

M50LPW040
Table 13. Status Register Bits
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey
different information and errors on the operation.
To read the Status Register the Read Status
Register command can be issued. The Status
Register is automatically read after Program,
Erase and Program/Erase Resume commands
are issued. The Status Register can be read from
any address.
The Status Register bits are summarized in Table
13, Status Register Bits. Refer to Table 13 in con-
junction with the text descriptions below.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
14/36
Program active
Program suspended
Program completed successfully
Program failure due to V
Program failure due to Block Protection (LPC Interface only)
Program failure due to cell failure
Erase active
Block Erase suspended
Erase completed successfully
Erase failure due to V
Block Erase failure due to Block Protection (LPC Interface
only)
Erase failure due to failed cell(s)
PP
PP
Error
Operation
Error
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, V
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that a Block Erase oper-
ation has been suspended and is waiting to be
resumed. The Erase Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Pro-
gram/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctly; when the Erase Status bit is ‘1’ the Pro-
Bit 7
‘0’
‘1’
‘1’
‘1’
‘1’
‘0’
‘1’
‘1’
‘1’
‘1’
‘1’
‘1
Bit 6
X
X
X
X
X
X
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
(1)
(1)
(1)
(1)
(1)
(1)
Bit 5
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
Bit 4
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Bit 3
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
Bit 2
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Bit 1
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
PP