M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 3

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

current PC Chipsets; the M50LPW040 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
and PLCC32 packages and it is supplied with all
the bits erased (set to ’1’).
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Figure 4. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
A/A Mux
A/A Mux
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
LAD0
GPI1
GPI0
RFU
TBL
WP
ID2
ID1
ID0
9
M50LPW040
17
1
32
Table 1. Signal Names (LPC Interface) Memory
Note: 1. Pin 9 in the PLCC32, and Pin 21 in the TSOP40, may also
LAD0-LAD3
LFRAME
ID0-ID2
GPI0-GPI4
IC
RP
INIT
CLK
TBL
WP
RFU
V
V
V
NC
CC
PP
SS
1
25
be driven High or driven Low.
IC (V IL )
NC
NC
V SS
V CC
INIT
LFRAME
RFU
RFU
Input/Output Communications
Identification Inputs
Input Communication Frame
General Purpose Inputs
Interface Configuration
Interface Reset
CPU Reset
Clock
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
Ground
Not Connected Internally
IC (V IH )
NC
NC
V SS
V CC
G
W
RB
DQ7
A/A Mux
A/A Mux
M50LPW040
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