M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 4

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

M50LPW040
Table 2. Memory Identification Input Configuration
Low Pin Count (LPC) Signal Descriptions
For the Low Pin Count (LPC) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Input/Output Communications (LAD0-LAD3). All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (LFRAME). The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Commu-
nication Frame is Low, V
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, V
operation then the operation is aborted. When In-
put Communication Frame is High, V
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID2). The Identification
Inputs (ID0-ID2) allow to address up to 8
memories on a bus. The value on addresses A19-
A21 is compared to the hardware strapping on the
ID0-ID2 pins to select which memory is being
addressed. For an address bit to be ‘1’ the
correspondent ID pin can be left floating or driven
Low, V
with a value of R
correspondent ID pin must be driven High, V
there will be a leakage current of I
pin when pulled to V
By convention the boot memory must have ID0-
ID2 pins left floating or driven Low, V
value on A19-A21 and all additional memories
take sequential ID0-ID2 configuration, as shown in
Table 2.
General Purpose Inputs (GPI0-GPI4). The Gener-
al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg-
ister holds the values on these pins. The pins must
4/36
Memory Number
1 (Boot)
IL
; an internal pull-down resistor is included
2
3
4
5
6
7
8
IL
. For an address bit to be ‘0’ the
V
V
V
V
IH
IL
IL
IL
IL
; see Table 20.
or floating
or floating
or floating
or floating
ID2
V
V
V
V
IH
IH
IH
IH
IL
, on the rising edge of
LI2
IL
V
V
V
V
, during a bus
IL
IL
IL
IL
through each
IL
or floating
or floating
or floating
or floating
ID1
V
V
V
V
IH
and a ‘111’
IH
IH
IH
IH
, the cur-
IH
V
V
V
V
;
IL
IL
IL
IL
or floating
or floating
or floating
or floating
ID0
V
V
V
V
IH
IH
IH
IH
have stable data from before the start of the cycle
that reads the General Purpose Input Register un-
til after the cycle is complete. These pins must not
be left to float, they should be driven Low, V
High, V
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, V
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
included with a value of R
current of I
see Table 20.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, V
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
IH
.
LI2
IH
A21
, the memory is in normal operation.
1
1
1
1
0
0
0
0
through each pin when pulled to V
IH
IL
; to select the Address/Address
. An internal pull-down resistor is
IL
IL
, the memory is in Reset
A20
; there will be a leakage
1
1
0
0
1
1
0
0
A19
1
0
1
0
1
0
1
0
IL,
IH
or
;