M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 16

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

M50LPW040
Table 14. Low Pin Count Register Configuration Map
Note: 1. This map is referred to the boot memory (ID0-ID2 floating or driven, L
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Block Erase Command).
When the Write Lock Bit is set, ‘1’, the block is
write protected; any operations that attempt to
change the data in the block will fail and the Status
Register will report the error. When the Write Lock
Bit is reset, ‘0’, the block is not write protected
through the Lock Register and may be modified
unless write protected through some other means.
When V
tected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, V
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, V
Blocks (Blocks 0 to 6) are write protected and can-
not be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
16/36
T_MINUS01_LK
T_MINUS02_LK
T_MINUS03_LK
T_MINUS04_LK
T_MINUS05_LK
T_MINUS06_LK
T_MINUS07_LK
T_BLOCK_LK
Mnemonic
GPI_REG
PP
IL
, then the Top Block (Block 7) is write
is less than V
Top Block Lock Register (Block 7)
Top Block [-1] Lock Register (Block 6)
Top Block [-2] Lock Register (Block 5)
Top Block [-3] Lock Register (Block 4)
Top Block [-4] Lock Register (Block 3)
Top Block [-5] Lock Register (Block 2)
Top Block [-6] Lock Register (Block 1)
Top Block [-7] Lock Register (Block 0)
General Purpose Input Register
PPLK
all blocks are pro-
IL
, then the Main
Register Name
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
General Purpose Input Register
The General Purpose Input Register holds the
state of the General Purpose Input pins, GPI0-
GPI4. When this register is read, the state of these
pins is returned. This register is read-only and writ-
ing to it has no effect.
The signals on the General Purpose Input pins
should remain constant throughout the whole Bus
Read cycle in order to guarantee that the correct
data is read.
(1)
OW
, V
IL
and A19-A21 set to ‘1’).
FFBE0002h
FFBD0002h
FFBC0002h
FFBB0002h
FFBA0002h
FFBC0100h
FFBF0002h
FFB90002h
FFB80002h
Address
Memory
Default
Value
01h
01h
01h
01h
01h
01h
01h
01h
N/A
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R