AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 106
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3
Note:
19.2.3
19.2.4
106
ARM Request (16-bit)
Buffer (32 bits)
Data To ARM
Flash Access
Master Clock
When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the
third access FWS cycles, the fourth access one cycle, etc.
Code Fetch
AT91SAM7X512/256/128 Preliminary
Write Operations
Flash Commands
@Byte 0
3 Wait State Cycles
The internal memory area reserved for the embedded Flash can also be written through a write-
only latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap
around within the internal memory area address space and appear to be repeated 1024 times
within it.
Write operations can be prevented by programming the Memory Protection Unit of the product.
Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in the number of wait states equal to the number of wait states
for read operations + 1, except for FWS = 3 (see
The EFC offers a command set to manage programming the memory flash, locking and unlock-
ing lock sectors, consecutive programming and locking, and full Flash erasing.
Table 19-2.
Command
Write page
Set Lock Bit
Write Page and Lock
Clear Lock Bit
Erase all
Set General-purpose NVM Bit
Clear General-purpose NVM Bit
Set Security Bit
Bytes 0-3
Set of Commands
@2
0-1
3 Wait State Cycles
@4
2-3
Bytes 0-3
Bytes 4-7
@6
4-5
3 Wait State Cycles
@8
6-7
“MC Flash Mode Register” on page
Bytes 8-11
Bytes 4-7
Value
0x0B
0x0D
0x0F
0x01
0x02
0x03
0x04
0x08
@10
8-9 10-11
3 Wait State Cycles
@12
Mnemonic
WP
SLB
WPL
CLB
EA
SGPB
CGPB
SSB
6120H–ATARM–17-Feb-09
Bytes 12-15
Bytes 8-11
114).
12-13
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