AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 423

no-image

AT91SAM7X128

Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet

Specifications of AT91SAM7X128

Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X128-AU
Manufacturer:
ATMEL
Quantity:
1 045
Part Number:
AT91SAM7X128-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT91SAM7X128-AU-999
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT91SAM7X128-CU-999
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128B-AU
Manufacturer:
Atmel
Quantity:
1 929
Part Number:
AT91SAM7X128B-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128B-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
33. Pulse Width Modulation Controller (PWM)
33.1
33.2
6120H–ATARM–17-Feb-09
Overview
Block Diagram
The PWM macrocell controls several channels independently. Each channel controls one
square output waveform. Characteristics of the output waveform such as period, duty-cycle and
polarity are configurable through the user interface. Each channel selects and uses one of the
clocks provided by the clock generator. The clock generator provides several clocks resulting
from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a
double buffering system in order to prevent an unexpected output waveform while modifying the
period or the duty-cycle.
Figure 33-1. Pulse Width Modulation Controller Block Diagram
PMC
MCK
AT91SAM7X512/256/128 Preliminary
Clock Generator
Channel
Channel
Selector
Selector
PWMx
PWM0
Clock
Clock
APB Interface
Controller
PWM
Duty Cycle
Duty Cycle
Counter
Counter
Update
Update
APB
Period
Period
Comparator
Comparator
Interrupt Generator
PIO
AIC
PWM0
PWM0
PWMx
PWMx
423

Related parts for AT91SAM7X128