AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 185
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AT91SAM7X128
Manufacturer Part Number
AT91SAM7X128
Description
MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
Manufacturer
Atmel
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Ram Size
32 KB
Program Memory Size
128 KB
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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6120H–ATARM–17-Feb-09
Note:
• If a new value for CSS field corresponds to PLL Clock,
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
5. Selection of Programmable clocks
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY
bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet.
The user must wait for MCKRDY bit to be set again before using the Master and Processor
Clocks.
Code Example:
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and
PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR
registers. Depending on the system used, 4 Programmable clocks can be enabled or dis-
abled. The PMC_SCSR provides a clear indication as to which Programmable clock is
enabled. By default all Programmable clocks are disabled.
PMC_PCKx registers are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options
are available: main clock, slow clock, PLLCK. By default, the clock source selected is slow
clock.
The PRES field is used to control the Programmable clock prescaler. It is possible to choose
between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in
CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again,
LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For fur-
ther information, see
AT91SAM7X512/256/128 Preliminary
Section 25.8.2
.
“Clock Switching Waveforms” on page 187
.
185
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