IDT82P2821BHG IDT, Integrated Device Technology Inc, IDT82P2821BHG Datasheet - Page 51

• Manufacturer Part Number: IDT82P2821BHG
• Description: IC LINE INTERFACE UNIT 640-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2821BHG

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1703; 82P2821BHG

Functional Description
IDT82P2821
Figure-30 Automatic Error Counter Updating
No
Data in the Error Counter transfers
Automatic Error Counter Updating
to the ERRCH & ERRCL registers
TMOV_IS is cleared after a '1' is
The Error Counter is cleared
Read the ERRCH & ERRCL
registers in the next second
One second expired?
(TMOV_IS = 1 ?)
(CNT_MD = 1)
written to it
Counting
Yes
same process
in the next
repeat the
second
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
51
3.5.6.2 Manual Error Counter Updating
updated manually.
ERR,...), the Error Counter transfers the accumulated error numbers to
the ERRCH and ERRCL registers and the Error Counter will be cleared
to start a new round counting. The ERRCH and ERRCL registers should
be read in the next round of error counting, otherwise they will be over-
written.
error to be accumulated, the registers will be overflowed. The overflow is
indicated by the CNTOV_IS bit (b0, INTS2,...) and will induce an inter-
rupt reported by INT if not masked by the CNTOV_IM (b0, INTM2,...).
Figure-31.
When the CNT_MD bit (b1, ERR,...) is ‘0’, the Error Counter is
When there is a transition from ‘0’ to ‘1’ on the CNT_STOP bit (b0,
When the ERRCH and ERRCL registers are all ‘1’s and there is still
The process of manual Error Counter updating is illustrated in
Figure-31 Manual Error Counter Updating
No
Data in the Error Counter transfers
to the ERRCH & ERRCL registers
Manual Error Counter Updating
The Error Counter is cleared
Read the ERRCH & ERRCL
registers in the next round
A transition from '0' to
'1' on CNT_STOP ?
(CNT_MD = 0)
Counting
Yes
February 6, 2009
(CNT_STOP
next round)
repeat the
process in
before the
the next
must be
cleared
round
same