AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 101
AT32UC3B0256
Manufacturer Part Number
AT32UC3B0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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- Current page: 101 of 684
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13.6.2
Figure 13-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge
Figure 13-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge
32059L–AVR32–01/2012
EXTINTn/NMI
EXTINTn/NMI
FILTER off
FILTER on
FILTER off
FILTER on
ISR.INTn:
ISR.INTn:
ISR.INTn:
ISR.INTn:
CLK_SYNC
CLK_SYNC
Synchronization and Filtering of External Interrupts
gate to the interrupt controller. However, the corresponding bit in ISR will be set, and
EIC_WAKE will be set.
If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an
external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR.
In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so
spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The syn-
chronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the
interrupt controller by two cycles of CLK_SYNC, see
on page 101
It is also possible to apply a filter on EXTINTn by writing a one to INTn bit in the FILTER register.
This filter is a majority voter, if the condition for an interrupt is true for more than one of the latest
three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of
the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see
page 101
and
for examples (FILTER off).
Figure 13-3 on page 101
for examples (FILTER on).
Figure 13-2 on page 101
and
Figure 13-2 on
Figure 13-3
101
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