AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 224

• Manufacturer Part Number: AT32UC3B0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10.6
Figure 19-9. Master Read with One Data Byte
Figure 19-10. Master Read with Multiple Data Bytes
19.10.7
32059L–AVR32–01/2012
TXCOMP
RXRDY
TWD
Master Receiver Mode
Internal Address
S
Write START Bit
DADR
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in MMR). During the acknowledge
clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it
down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (RHR). The RXRDY bit is reset when reading the RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without IADR, the STOP bit must be set after the next-to-last data received.
See
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
TXCOMP
RXRDY
R
Figure
TWD
A
19-10. For Internal Address usage see
S
DATA n
Write START &
STOP Bit
DADR
Read RHR
A
DATA n
DATA (n+1)
R
A
A
DATA (n+1)
Read RHR
DATA
DATA (n+m)-1
Figure
”Internal Address” on page
Read RHR
N
19-9. When a multiple data byte read is
DATA (n+m)-1
P
A
Read RHR
after next-to-last data read
DATA (n+m)
Write STOP Bit
Figure
224.
19-9. When the
N
DATA (n+m)
Read RHR
P
224