AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 216

• Manufacturer Part Number: AT32UC3B0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.8.9
Name:
Access Type:
Offset:
Reset Value:
• DLYBCT: Delay Between Consecutive Transfers
• DLYBS: Delay Before SPCK
• ISCBR: Serial Clock Baud Rate
32059L–AVR32–01/2012
31
23
15
7
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
I
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
Writing 0 to the SCBR field is forbidden. Triggering a transfer while SCBR is 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to write it at a valid value before performing the first transfer.
IIf a clock divider (SCBRn) is set to 1 and the other SCBR differ from 1, access on CSn is correct but no correct access will be
possible on others CS.
Delay Between Consecutive Transfers
Delay Before SPCK
SPCK Baudrate
Chip Select Register n
30
22
14
CSRn
Read/Write
0x30 +0x04*n
0x00000000
6
=
BITS
CLKSPI
---------------------
=
SCBR
-------------------- -
CLKSPI
DLYBS
29
21
13
5
=
32
----------------------------------- -
28
20
12
4
CLKSPI
×
DLYBCT
DLYBCT
DLYBS
SCBR
CSAAT
27
19
11
3
CSNAAT
26
18
10
2
NCPHA
25
17
9
1
CPOL
24
16
8
0
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