AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 311

• Manufacturer Part Number: AT32UC3B0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 21-18. FSK Modulator Output
21.6.4.6
21.6.4.7
32059L–AVR32–01/2012
Uptstream Frequencies
unipolar output
FSK Modulator
default polarity
[F0, F0+offset]
NRZ stream
Manchester
Receiver Operations
encoded
Synchronous Receiver
Output
data
Txd
1
In synchronous mode (SYNC=1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start bit. Configuration bits
and fields are the same as in asynchronous mode.
Figure 21-19. Synchronous Mode Character Reception
When a character reception is completed, it is transferred to the Received Character field in the
Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status
Register (CSR.RXRDY) is set. If RXRDY is already set, RHR will be overwritten and the Overrun
Error bit (CSR.OVRE) is set. Reading RHR will clear CSR.RXRDY, and writing a one to the
Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE.
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Sampling
Clock
RXD
Start
0
D0
D1
D2
0
D3
D4
D5
D6
D7
1
Parity Bit
Stop Bit
311