AT32UC3B0256 Atmel Corporation, AT32UC3B0256 Datasheet - Page 562
AT32UC3B0256
Manufacturer Part Number
AT32UC3B0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 562 of 684
- Download datasheet (11Mb)
26.5.2
26.5.3
26.6
26.6.1
26.6.2
32059L–AVR32–01/2012
Functional Description
Clocks
Interrupts
How to Initialize the Module
Data Format
The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before
using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is
enabled in the Power Manager.
The ABDAC needs a separate clock for the D/A conversion operation. This clock,
GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre-
quency must be as follow:
where f
GCLK_ABDAC clock must have a frequency of 12.288MHz.
The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other.
The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC
interrupt requires the interrupt controller to be programmed first.
In order to use the Audio Bitstream DAC the product dependencies given in
page 561
and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.
The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream
DAC Control Register (CR.EN).
The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be
set whenever the ABDAC is ready to receive a new sample. A new sample value should be writ-
ten to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the
Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writ-
ing one to the corresponding bits in the Interrupt Clear Register (ICR).
The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can
be written to the least and most significant halfword of the Sample Data Register (SDR),
respectively.
An input value of 0x7FFF will result in an output voltage of approximately:
An Input value of 0x8000 will result in an output value of approximately:
s
is the samping rate of the data stream to convert. For f
must be resolved. Particular attention should be given to the configuration of clocks
V
V
OUT
OUT
(
(
0 x 7 FFF
0 x 8000
)
)
f
GCLK
≈
≈
--------- - VDDIO
128
--------- - VDDIO
128
38
90
=
⋅
⋅
256 f
×
=
=
S
--------- - 3 3
128
--------- - 3 3
128
38
90
⋅
⋅
,
,
≈
≈
0
2
s
,
,
= 48 kHz this means that the
98 V
32 V
Section 26.5 on
562
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