AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 103

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AT89C51CC01

Manufacturer Part Number
AT89C51CC01
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C51CC01

Flash (kbytes)
32 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
34
Uart
1
Can
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
1.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART/CAN
Watchdog
Yes

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4129N–CAN–03/08
Table 69. CANIE2 Register
CANIE2 (S:C3h)
CAN Enable Interrupt Message Object Registers 2
Reset Value = 0000 0000b
Table 70. CANBT1 Register
CANBT1 (S:B4h)
CAN Bit Timing Registers 1
Note:
No default value after reset.
Number
Number
IECH 7
Bit
Bit
7-0
6-1
7
7
-
7
0
The CAN controller bit timing registers must be accessed only if the CAN controller is dis-
abled with the ENA bit of the CANGCON register set to 0.
See Figure 48.
Bit Mnemonic Description
Bit Mnemonic Description
IECH 6
BRP 5
IECH7:0
BRP5:0
6
6
-
-
IECH 5
Enable interrupt by Message Object
0 - disable IT.
1 - enable IT.
IECH7:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 and 2.
BRP 4
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud rate prescaler
The period of the CAN controller system clock Tscl is programmable and
determines the individual bit timing.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
5
IECH 4
BRP 3
4
4
Tscl =
IECH 3
BRP 2
3
3
BRP[5..0] + 1
Fcan
IECH 2
BRP 1
2
2
IECH 1
BRP 0
1
1
IECH 0
0
0
-
103

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