AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 137

• Manufacturer Part Number: AT89C51CC01
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC01

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 1.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

4129N–CAN–03/08
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register. This register also contains a global disable bit
which must be cleared to disable all the interrupts at the same time.
Each interrupt source can also be individually programmed to one of four priority levels
by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the
bit values and priority levels associated with each combination.
Table 113. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt but not by another
low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of the higher priority level is serviced. If interrupt requests of the same priority
level are received simultaneously, an internal polling sequence determines which
request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence, see Table 114.
Table 114. Interrupt Priority Within level
CAN Timer Overflow (OVRTIM)
CAN (Txok, Rxok, Err or
external interrupt (INT0)
external interrupt (INT1)
PCA (CF or CCFn)
Interrupt Name
UART (RI or TI)
Timer 0 (TF0)
Timer 1 (TF1)
Timer 2 (TF2)
ADC (ADCI)
OvrBuf)
IPH.x
0
0
1
1
Interrupt Address Vector
000Bh
001Bh
002Bh
003Bh
004Bh
0003h
0013h
0033h
0023h
0043h
IPL.x
0
1
0
1
Interrupt Number
10
1
2
3
4
7
5
6
8
9
Interrupt Level Priority
3 (Highest)
0 (Lowest)
1
2
Polling Priority
10
1
2
3
4
5
6
7
8
9
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