AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 85
AT89C51CC01
Manufacturer Part Number
AT89C51CC01
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C51CC01.pdf
(167 pages)
2.AT89C51CC01.pdf
(12 pages)
3.AT89C51CC01.pdf
(32 pages)
4.AT89C51CC01.pdf
(29 pages)
Specifications of AT89C51CC01
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
34
Uart
1
Can
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
1.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART/CAN
Watchdog
Yes
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4129N–CAN–03/08
•
To enable an interrupt on message object error:
•
•
•
To enable an interrupt on general error:
•
•
To enable an interrupt on Buffer-full condition:
•
•
To enable an interrupt when Timer overruns:
•
When an interrupt occurs, the corresponding message object bit is set in the SIT
register.
To acknowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or
CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application.
When the CAN node is in transmission and detects a Form Error in its frame, a bit Error
will also be raised. Consequently, two consecutive interrupts can occur, both due to the
same error.
When a message object error occurs and is set in CANSTCH register, no general error
are set in CANGIE register.
Enable reception interrupt, ENRX.
Enable General CAN IT in the interrupt system register,
Enable interrupt by message object, EICHi,
Enable interrupt on error, ENERCH.
Enable General CAN IT in the interrupt system register,
Enable interrupt on error, ENERG.
Enable General CAN IT in the interrupt system register,
Enable interrupt on Buffer full, ENBUF.
Enable Overrun IT in the interrupt system register.
85